]> sigrok.org Git - libsigrok.git/blame - hardware/openbench-logic-sniffer/ols.c
ols: fixed *ctx null dereferences that would SEGFAULT on probing for a OLS or attempt...
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
b7f09cf8
UH
41#include "sigrok.h"
42#include "sigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
ffedd0bf 49static int hwcaps[] = {
5a2326a7
UH
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 54 SR_HWCAP_RLE,
43fc7885 55 0,
a1bb33af
UH
56};
57
d261dbbf 58/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 59static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
4fe9a6da 95/* default supported samplerates, can be overridden by device metadata */
60679b18 96static struct sr_samplerates samplerates = {
c9140419 97 SR_HZ(10),
59df0c77 98 SR_MHZ(200),
c9140419
UH
99 SR_HZ(1),
100 NULL,
a1bb33af
UH
101};
102
d68e2d1a
UH
103/* List of struct sr_serial_dev_inst */
104static GSList *dev_insts = NULL;
a1bb33af 105
6937bb75 106static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
107{
108 char buf[1];
109
b08024a8 110 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 111 buf[0] = command;
2119ab03 112 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 113 return SR_ERR;
a1bb33af 114
e46b8fb1 115 return SR_OK;
a1bb33af
UH
116}
117
6937bb75 118static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
2119ab03 128 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
ea9cfed7 134static int configure_probes(struct context *ctx, GSList *probes)
a1bb33af 135{
1afe8989 136 struct sr_probe *probe;
a1bb33af 137 GSList *l;
6937bb75 138 int probe_bit, stage, i;
a1bb33af
UH
139 char *tc;
140
ea9cfed7 141 ctx->probe_mask = 0;
43fc7885 142 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
ea9cfed7
UH
143 ctx->trigger_mask[i] = 0;
144 ctx->trigger_value[i] = 0;
a1bb33af
UH
145 }
146
ea9cfed7 147 ctx->num_stages = 0;
43fc7885 148 for (l = probes; l; l = l->next) {
1afe8989 149 probe = (struct sr_probe *)l->data;
43fc7885 150 if (!probe->enabled)
6937bb75
BV
151 continue;
152
43fc7885
UH
153 /*
154 * Set up the probe mask for later configuration into the
155 * flag register.
156 */
a1bb33af 157 probe_bit = 1 << (probe->index - 1);
ea9cfed7 158 ctx->probe_mask |= probe_bit;
6937bb75 159
a803c0db 160 if (!probe->trigger)
6937bb75
BV
161 continue;
162
43fc7885 163 /* Configure trigger mask and value. */
6937bb75 164 stage = 0;
43fc7885 165 for (tc = probe->trigger; tc && *tc; tc++) {
ea9cfed7 166 ctx->trigger_mask[stage] |= probe_bit;
43fc7885 167 if (*tc == '1')
ea9cfed7 168 ctx->trigger_value[stage] |= probe_bit;
6937bb75 169 stage++;
43fc7885
UH
170 if (stage > 3)
171 /*
172 * TODO: Only supporting parallel mode, with
173 * up to 4 stages.
174 */
e46b8fb1 175 return SR_ERR;
a1bb33af 176 }
ea9cfed7
UH
177 if (stage > ctx->num_stages)
178 ctx->num_stages = stage;
a1bb33af
UH
179 }
180
e46b8fb1 181 return SR_OK;
a1bb33af
UH
182}
183
a803c0db 184static uint32_t reverse16(uint32_t in)
6937bb75
BV
185{
186 uint32_t out;
187
a803c0db
BV
188 out = (in & 0xff) << 8;
189 out |= (in & 0xff00) >> 8;
190 out |= (in & 0xff0000) << 8;
191 out |= (in & 0xff000000) >> 8;
192
193 return out;
194}
195
196static uint32_t reverse32(uint32_t in)
197{
198 uint32_t out;
199
200 out = (in & 0xff) << 24;
201 out |= (in & 0xff00) << 8;
202 out |= (in & 0xff0000) >> 8;
203 out |= (in & 0xff000000) >> 24;
204
205 return out;
6937bb75
BV
206}
207
ea9cfed7 208static struct context *ols_dev_new(void)
4fe9a6da 209{
ea9cfed7 210 struct context *ctx;
4fe9a6da 211
ea9cfed7
UH
212 /* TODO: Is 'ctx' ever g_free()'d? */
213 if (!(ctx = g_try_malloc0(sizeof(struct context)))) {
214 sr_err("ols: %s: ctx malloc failed", __func__);
b53738ba
UH
215 return NULL;
216 }
217
ea9cfed7
UH
218 ctx->trigger_at = -1;
219 ctx->probe_mask = 0xffffffff;
220 ctx->cur_samplerate = SR_KHZ(200);
221 ctx->serial = NULL;
4fe9a6da 222
ea9cfed7 223 return ctx;
4fe9a6da
BV
224}
225
d68e2d1a 226static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 227{
d68e2d1a 228 struct sr_dev_inst *sdi;
ea9cfed7 229 struct context *ctx;
4fe9a6da
BV
230 uint32_t tmp_int;
231 uint8_t key, type, token;
bb7ef793 232 GString *tmp_str, *devname, *version;
4fe9a6da
BV
233 gchar tmp_c;
234
d3683c42 235 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
ea9cfed7
UH
236 ctx = ols_dev_new();
237 sdi->priv = ctx;
4fe9a6da 238
bb7ef793 239 devname = g_string_new("");
4fe9a6da
BV
240 version = g_string_new("");
241
242 key = 0xff;
243 while (key) {
244 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
245 break;
246 type = key >> 5;
247 token = key & 0x1f;
248 switch (type) {
249 case 0:
250 /* NULL-terminated string */
251 tmp_str = g_string_new("");
252 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
253 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
254 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
255 key, tmp_str->str);
4fe9a6da
BV
256 switch (token) {
257 case 0x01:
258 /* Device name */
bb7ef793 259 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
260 break;
261 case 0x02:
262 /* FPGA firmware version */
263 if (version->len)
264 g_string_append(version, ", ");
265 g_string_append(version, "FPGA version ");
266 g_string_append(version, tmp_str->str);
267 break;
268 case 0x03:
269 /* Ancillary version */
270 if (version->len)
271 g_string_append(version, ", ");
272 g_string_append(version, "Ancillary version ");
273 g_string_append(version, tmp_str->str);
274 break;
275 default:
b08024a8
UH
276 sr_info("ols: unknown token 0x%.2x: '%s'",
277 token, tmp_str->str);
4fe9a6da
BV
278 break;
279 }
280 g_string_free(tmp_str, TRUE);
281 break;
282 case 1:
283 /* 32-bit unsigned integer */
284 if (serial_read(fd, &tmp_int, 4) != 4)
285 break;
286 tmp_int = reverse32(tmp_int);
b08024a8
UH
287 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
288 key, tmp_int);
4fe9a6da
BV
289 switch (token) {
290 case 0x00:
291 /* Number of usable probes */
ea9cfed7 292 ctx->num_probes = tmp_int;
4fe9a6da
BV
293 break;
294 case 0x01:
295 /* Amount of sample memory available (bytes) */
ea9cfed7 296 ctx->max_samples = tmp_int;
4fe9a6da
BV
297 break;
298 case 0x02:
299 /* Amount of dynamic memory available (bytes) */
300 /* what is this for? */
301 break;
302 case 0x03:
303 /* Maximum sample rate (hz) */
ea9cfed7 304 ctx->max_samplerate = tmp_int;
4fe9a6da
BV
305 break;
306 case 0x04:
307 /* protocol version */
ea9cfed7 308 ctx->protocol_version = tmp_int;
4fe9a6da
BV
309 break;
310 default:
b08024a8
UH
311 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
312 token, tmp_int);
4fe9a6da
BV
313 break;
314 }
315 break;
316 case 2:
317 /* 8-bit unsigned integer */
318 if (serial_read(fd, &tmp_c, 1) != 1)
319 break;
b08024a8
UH
320 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
321 key, tmp_c);
4fe9a6da
BV
322 switch (token) {
323 case 0x00:
324 /* Number of usable probes */
ea9cfed7 325 ctx->num_probes = tmp_c;
4fe9a6da
BV
326 break;
327 case 0x01:
328 /* protocol version */
ea9cfed7 329 ctx->protocol_version = tmp_c;
4fe9a6da
BV
330 break;
331 default:
b08024a8
UH
332 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
333 token, tmp_c);
4fe9a6da
BV
334 break;
335 }
336 break;
337 default:
338 /* unknown type */
339 break;
340 }
341 }
342
bb7ef793 343 sdi->model = devname->str;
4fe9a6da 344 sdi->version = version->str;
bb7ef793 345 g_string_free(devname, FALSE);
4fe9a6da
BV
346 g_string_free(version, FALSE);
347
348 return sdi;
349}
350
bb7ef793 351static int hw_init(const char *devinfo)
a1bb33af 352{
d68e2d1a 353 struct sr_dev_inst *sdi;
ea9cfed7 354 struct context *ctx;
a1bb33af 355 GSList *ports, *l;
4fe9a6da 356 GPollFD *fds, probefd;
6937bb75 357 int devcnt, final_devcnt, num_ports, fd, ret, i;
bb7ef793 358 char buf[8], **dev_names, **serial_params;
a1bb33af 359
c0a4b971
UH
360 final_devcnt = 0;
361
bb7ef793
UH
362 if (devinfo)
363 ports = g_slist_append(NULL, g_strdup(devinfo));
a1bb33af 364 else
43fc7885 365 /* No specific device given, so scan all serial ports. */
a1bb33af
UH
366 ports = list_serial_ports();
367
368 num_ports = g_slist_length(ports);
c0a4b971
UH
369
370 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
371 sr_err("ols: %s: fds malloc failed", __func__);
372 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
373 }
374
bb7ef793
UH
375 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
376 sr_err("ols: %s: dev_names malloc failed", __func__);
c0a4b971
UH
377 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
378 }
379
380 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
381 sr_err("ols: %s: serial_params malloc failed", __func__);
bb7ef793 382 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
c0a4b971
UH
383 }
384
a1bb33af 385 devcnt = 0;
43fc7885
UH
386 for (l = ports; l; l = l->next) {
387 /* The discovery procedure is like this: first send the Reset
388 * command (0x00) 5 times, since the device could be anywhere
389 * in a 5-byte command. Then send the ID command (0x02).
390 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
391 * have a match.
392 *
393 * Since it may take the device a while to respond at 115Kb/s,
394 * we do all the sending first, then wait for all of them to
395 * respond with g_poll().
a1bb33af 396 */
b08024a8 397 sr_info("ols: probing %s...", (char *)l->data);
d02a535e 398 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
43fc7885 399 if (fd != -1) {
d02a535e
BV
400 serial_params[devcnt] = serial_backup_params(fd);
401 serial_set_params(fd, 115200, 8, 0, 1, 2);
e46b8fb1 402 ret = SR_OK;
43fc7885
UH
403 for (i = 0; i < 5; i++) {
404 if ((ret = send_shortcommand(fd,
e46b8fb1 405 CMD_RESET)) != SR_OK) {
43fc7885 406 /* Serial port is not writable. */
6937bb75
BV
407 break;
408 }
a1bb33af 409 }
e46b8fb1 410 if (ret != SR_OK) {
43fc7885
UH
411 serial_restore_params(fd,
412 serial_params[devcnt]);
d02a535e 413 serial_close(fd);
6937bb75 414 continue;
d02a535e 415 }
6937bb75
BV
416 send_shortcommand(fd, CMD_ID);
417 fds[devcnt].fd = fd;
418 fds[devcnt].events = G_IO_IN;
bb7ef793 419 dev_names[devcnt] = g_strdup(l->data);
6937bb75 420 devcnt++;
a1bb33af 421 }
133a37bf 422 g_free(l->data);
a1bb33af
UH
423 }
424
5b15b41e
PS
425 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
426 usleep(10000);
a1bb33af 427
a1bb33af 428 g_poll(fds, devcnt, 1);
4fe9a6da 429
43fc7885 430 for (i = 0; i < devcnt; i++) {
4fe9a6da
BV
431 if (fds[i].revents != G_IO_IN)
432 continue;
433 if (serial_read(fds[i].fd, buf, 4) != 4)
434 continue;
435 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
436 continue;
437
438 /* definitely using the OLS protocol, check if it supports
439 * the metadata command
440 */
441 send_shortcommand(fds[i].fd, CMD_METADATA);
442 probefd.fd = fds[i].fd;
443 probefd.events = G_IO_IN;
444 if (g_poll(&probefd, 1, 10) > 0) {
445 /* got metadata */
446 sdi = get_metadata(fds[i].fd);
447 sdi->index = final_devcnt;
13d0d269 448 ctx = sdi->priv;
4fe9a6da
BV
449 } else {
450 /* not an OLS -- some other board that uses the sump protocol */
d3683c42 451 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
4fe9a6da 452 "Sump", "Logic Analyzer", "v1.0");
ea9cfed7
UH
453 ctx = ols_dev_new();
454 ctx->num_probes = 32;
455 sdi->priv = ctx;
a1bb33af 456 }
ea9cfed7 457 ctx->serial = sr_serial_dev_inst_new(dev_names[i], -1);
d68e2d1a 458 dev_insts = g_slist_append(dev_insts, sdi);
4fe9a6da
BV
459 final_devcnt++;
460 serial_close(fds[i].fd);
461 fds[i].fd = 0;
4fe9a6da
BV
462 }
463
464 /* clean up after all the probing */
465 for (i = 0; i < devcnt; i++) {
43fc7885 466 if (fds[i].fd != 0) {
d02a535e
BV
467 serial_restore_params(fds[i].fd, serial_params[i]);
468 serial_close(fds[i].fd);
6937bb75 469 }
133a37bf 470 g_free(serial_params[i]);
bb7ef793 471 g_free(dev_names[i]);
a1bb33af
UH
472 }
473
c0a4b971 474 g_free(serial_params);
bb7ef793
UH
475hw_init_free_dev_names:
476 g_free(dev_names);
c0a4b971
UH
477hw_init_free_fds:
478 g_free(fds);
479hw_init_free_ports:
a1bb33af
UH
480 g_slist_free(ports);
481
482 return final_devcnt;
483}
484
e7eb703f 485static int hw_dev_open(int dev_index)
a1bb33af 486{
d68e2d1a 487 struct sr_dev_inst *sdi;
ea9cfed7 488 struct context *ctx;
a1bb33af 489
bb7ef793 490 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
e46b8fb1 491 return SR_ERR;
a1bb33af 492
ea9cfed7 493 ctx = sdi->priv;
69890f73 494
ea9cfed7
UH
495 ctx->serial->fd = serial_open(ctx->serial->port, O_RDWR);
496 if (ctx->serial->fd == -1)
e46b8fb1 497 return SR_ERR;
a1bb33af 498
5a2326a7 499 sdi->status = SR_ST_ACTIVE;
a1bb33af 500
e46b8fb1 501 return SR_OK;
a1bb33af
UH
502}
503
e7eb703f 504static int hw_dev_close(int dev_index)
a1bb33af 505{
d68e2d1a 506 struct sr_dev_inst *sdi;
ea9cfed7 507 struct context *ctx;
a1bb33af 508
bb7ef793 509 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
697785d1 510 sr_err("ols: %s: sdi was NULL", __func__);
0abee507 511 return SR_ERR_BUG;
697785d1 512 }
a1bb33af 513
ea9cfed7 514 ctx = sdi->priv;
69890f73 515
697785d1 516 /* TODO */
ea9cfed7
UH
517 if (ctx->serial->fd != -1) {
518 serial_close(ctx->serial->fd);
519 ctx->serial->fd = -1;
5a2326a7 520 sdi->status = SR_ST_INACTIVE;
a1bb33af 521 }
697785d1
UH
522
523 return SR_OK;
a1bb33af
UH
524}
525
57ab7d9f 526static int hw_cleanup(void)
a1bb33af
UH
527{
528 GSList *l;
d68e2d1a 529 struct sr_dev_inst *sdi;
ea9cfed7 530 struct context *ctx;
57ab7d9f 531 int ret = SR_OK;
a1bb33af 532
8722c31e 533 /* Properly close and free all devices. */
d68e2d1a 534 for (l = dev_insts; l; l = l->next) {
57ab7d9f
UH
535 if (!(sdi = l->data)) {
536 /* Log error, but continue cleaning up the rest. */
537 sr_err("ols: %s: sdi was NULL, continuing", __func__);
538 ret = SR_ERR_BUG;
539 continue;
540 }
ea9cfed7 541 if (!(ctx = sdi->priv)) {
57ab7d9f
UH
542 /* Log error, but continue cleaning up the rest. */
543 sr_err("ols: %s: sdi->priv was NULL, continuing",
544 __func__);
545 ret = SR_ERR_BUG;
546 continue;
547 }
548 /* TODO: Check for serial != NULL. */
ea9cfed7
UH
549 if (ctx->serial->fd != -1)
550 serial_close(ctx->serial->fd);
551 sr_serial_dev_inst_free(ctx->serial);
d3683c42 552 sr_dev_inst_free(sdi);
a1bb33af 553 }
d68e2d1a
UH
554 g_slist_free(dev_insts);
555 dev_insts = NULL;
57ab7d9f
UH
556
557 return ret;
a1bb33af
UH
558}
559
5097b0d0 560static void *hw_dev_info_get(int dev_index, int dev_info_id)
a1bb33af 561{
d68e2d1a 562 struct sr_dev_inst *sdi;
ea9cfed7 563 struct context *ctx;
a1bb33af
UH
564 void *info;
565
bb7ef793 566 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
a1bb33af 567 return NULL;
ea9cfed7 568 ctx = sdi->priv;
a1bb33af
UH
569
570 info = NULL;
bb7ef793 571 switch (dev_info_id) {
1d9a8a5f 572 case SR_DI_INST:
a1bb33af
UH
573 info = sdi;
574 break;
5a2326a7 575 case SR_DI_NUM_PROBES:
a1bb33af
UH
576 info = GINT_TO_POINTER(NUM_PROBES);
577 break;
464d12c7
KS
578 case SR_DI_PROBE_NAMES:
579 info = probe_names;
580 break;
5a2326a7 581 case SR_DI_SAMPLERATES:
a1bb33af
UH
582 info = &samplerates;
583 break;
5a2326a7 584 case SR_DI_TRIGGER_TYPES:
43fc7885 585 info = (char *)TRIGGER_TYPES;
a1bb33af 586 break;
5a2326a7 587 case SR_DI_CUR_SAMPLERATE:
ea9cfed7 588 info = &ctx->cur_samplerate;
a1bb33af
UH
589 break;
590 }
591
592 return info;
593}
594
e7eb703f 595static int hw_dev_status_get(int dev_index)
a1bb33af 596{
d68e2d1a 597 struct sr_dev_inst *sdi;
a1bb33af 598
bb7ef793 599 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
5a2326a7 600 return SR_ST_NOT_FOUND;
a1bb33af
UH
601
602 return sdi->status;
603}
604
ffedd0bf 605static int *hw_hwcap_get_all(void)
a1bb33af 606{
ffedd0bf 607 return hwcaps;
a1bb33af
UH
608}
609
a9a245b4 610static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 611{
ea9cfed7 612 struct context *ctx;
a1bb33af 613
ea9cfed7
UH
614 ctx = sdi->priv;
615 if (ctx->max_samplerate) {
616 if (samplerate > ctx->max_samplerate)
4fe9a6da
BV
617 return SR_ERR_SAMPLERATE;
618 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 619 return SR_ERR_SAMPLERATE;
a1bb33af 620
43fc7885 621 if (samplerate > CLOCK_RATE) {
ea9cfed7
UH
622 ctx->flag_reg |= FLAG_DEMUX;
623 ctx->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 624 } else {
ea9cfed7
UH
625 ctx->flag_reg &= ~FLAG_DEMUX;
626 ctx->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 627 }
a1bb33af 628
7583b99d
GM
629 /* Calculate actual samplerate used and complain if it is different
630 * from the requested.
631 */
ea9cfed7
UH
632 ctx->cur_samplerate = CLOCK_RATE / (ctx->cur_samplerate_divider + 1);
633 if (ctx->flag_reg & FLAG_DEMUX)
634 ctx->cur_samplerate *= 2;
635 if (ctx->cur_samplerate != samplerate)
133a37bf 636 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
ea9cfed7 637 PRIu64, samplerate, ctx->cur_samplerate);
7583b99d 638
e46b8fb1 639 return SR_OK;
a1bb33af
UH
640}
641
a9a245b4 642static int hw_dev_config_set(int dev_index, int hwcap, void *value)
a1bb33af 643{
d68e2d1a 644 struct sr_dev_inst *sdi;
ea9cfed7 645 struct context *ctx;
a1bb33af
UH
646 int ret;
647 uint64_t *tmp_u64;
648
bb7ef793 649 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
e46b8fb1 650 return SR_ERR;
ea9cfed7 651 ctx = sdi->priv;
a1bb33af 652
5a2326a7 653 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 654 return SR_ERR;
a1bb33af 655
ffedd0bf 656 switch (hwcap) {
5a2326a7 657 case SR_HWCAP_SAMPLERATE:
ee61b340 658 ret = set_samplerate(sdi, *(uint64_t *)value);
a803c0db 659 break;
5a2326a7 660 case SR_HWCAP_PROBECONFIG:
ea9cfed7 661 ret = configure_probes(ctx, (GSList *)value);
a803c0db 662 break;
5a2326a7 663 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 664 tmp_u64 = value;
574ce498 665 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 666 return SR_ERR;
ea9cfed7 667 if (*tmp_u64 > ctx->max_samples)
133a37bf 668 sr_err("ols: sample limit exceeds hw max");
ea9cfed7
UH
669 ctx->limit_samples = *tmp_u64;
670 sr_info("ols: sample limit %" PRIu64, ctx->limit_samples);
e46b8fb1 671 ret = SR_OK;
a803c0db 672 break;
5a2326a7 673 case SR_HWCAP_CAPTURE_RATIO:
ea9cfed7
UH
674 ctx->capture_ratio = *(uint64_t *)value;
675 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) {
676 ctx->capture_ratio = 0;
e46b8fb1 677 ret = SR_ERR;
43fc7885 678 } else
e46b8fb1 679 ret = SR_OK;
a803c0db 680 break;
3a4d09c0 681 case SR_HWCAP_RLE:
4d436e71 682 if (GPOINTER_TO_INT(value)) {
3a4d09c0 683 sr_info("ols: enabling RLE");
ea9cfed7 684 ctx->flag_reg |= FLAG_RLE;
3a4d09c0
GM
685 }
686 ret = SR_OK;
687 break;
a803c0db 688 default:
e46b8fb1 689 ret = SR_ERR;
43fc7885 690 }
a1bb33af
UH
691
692 return ret;
693}
694
1f9813eb 695static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 696{
b9c735a2 697 struct sr_datafeed_packet packet;
9c939c51 698 struct sr_datafeed_logic logic;
d68e2d1a 699 struct sr_dev_inst *sdi;
ea9cfed7 700 struct context *ctx;
4fe9a6da 701 GSList *l;
3a4d09c0
GM
702 int num_channels, offset, i, j;
703 unsigned char byte;
a1bb33af 704
ea9cfed7
UH
705 /* Find this device's ctx struct by its fd. */
706 ctx = NULL;
d68e2d1a 707 for (l = dev_insts; l; l = l->next) {
4fe9a6da 708 sdi = l->data;
13d0d269 709 ctx = sdi->priv;
ea9cfed7 710 if (ctx->serial->fd == fd) {
4fe9a6da
BV
711 break;
712 }
13d0d269 713 ctx = NULL;
4fe9a6da 714 }
ea9cfed7
UH
715 if (!ctx)
716 /* Shouldn't happen. */
4fe9a6da
BV
717 return TRUE;
718
ea9cfed7 719 if (ctx->num_transfers++ == 0) {
43fc7885
UH
720 /*
721 * First time round, means the device started sending data,
722 * and will not stop until done. If it stops sending for
723 * longer than it takes to send a byte, that means it's
724 * finished. We'll double that to 30ms to be sure...
a1bb33af 725 */
6f1be0a2 726 sr_source_remove(fd);
1f9813eb 727 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
ea9cfed7
UH
728 ctx->raw_sample_buf = g_try_malloc(ctx->limit_samples * 4);
729 if (!ctx->raw_sample_buf) {
730 sr_err("ols: %s: ctx->raw_sample_buf malloc failed",
c0a4b971
UH
731 __func__);
732 return FALSE;
733 }
a803c0db 734 /* fill with 1010... for debugging */
ea9cfed7 735 memset(ctx->raw_sample_buf, 0x82, ctx->limit_samples * 4);
a1bb33af
UH
736 }
737
6937bb75 738 num_channels = 0;
43fc7885 739 for (i = 0x20; i > 0x02; i /= 2) {
ea9cfed7 740 if ((ctx->flag_reg & i) == 0)
6937bb75 741 num_channels++;
43fc7885 742 }
6937bb75 743
3a4d09c0 744 if (revents == G_IO_IN) {
2119ab03 745 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
746 return FALSE;
747
baf1d714 748 /* Ignore it if we've read enough. */
ea9cfed7 749 if (ctx->num_samples >= ctx->limit_samples)
baf1d714 750 return TRUE;
3a4d09c0 751
ea9cfed7 752 ctx->sample[ctx->num_bytes++] = byte;
b08024a8 753 sr_dbg("ols: received byte 0x%.2x", byte);
ea9cfed7 754 if (ctx->num_bytes == num_channels) {
43fc7885 755 /* Got a full sample. */
b08024a8 756 sr_dbg("ols: received sample 0x%.*x",
ea9cfed7
UH
757 ctx->num_bytes * 2, *(int *)ctx->sample);
758 if (ctx->flag_reg & FLAG_RLE) {
43fc7885
UH
759 /*
760 * In RLE mode -1 should never come in as a
761 * sample, because bit 31 is the "count" flag.
43fc7885 762 */
ea9cfed7
UH
763 if (ctx->sample[ctx->num_bytes - 1] & 0x80) {
764 ctx->sample[ctx->num_bytes - 1] &= 0x7f;
baf1d714
UH
765 /*
766 * FIXME: This will only work on
767 * little-endian systems.
a1bb33af 768 */
ea9cfed7
UH
769 ctx->rle_count = *(int *)(ctx->sample);
770 sr_dbg("ols: RLE count = %d", ctx->rle_count);
771 ctx->num_bytes = 0;
3a4d09c0 772 return TRUE;
baf1d714 773 }
3a4d09c0 774 }
ea9cfed7
UH
775 ctx->num_samples += ctx->rle_count + 1;
776 if (ctx->num_samples > ctx->limit_samples) {
baf1d714 777 /* Save us from overrunning the buffer. */
ea9cfed7
UH
778 ctx->rle_count -= ctx->num_samples - ctx->limit_samples;
779 ctx->num_samples = ctx->limit_samples;
a1bb33af
UH
780 }
781
43fc7885
UH
782 if (num_channels < 4) {
783 /*
784 * Some channel groups may have been turned
785 * off, to speed up transfer between the
786 * hardware and the PC. Expand that here before
787 * submitting it over the session bus --
788 * whatever is listening on the bus will be
789 * expecting a full 32-bit sample, based on
790 * the number of probes.
6937bb75
BV
791 */
792 j = 0;
ea9cfed7 793 memset(ctx->tmp_sample, 0, 4);
43fc7885 794 for (i = 0; i < 4; i++) {
ea9cfed7 795 if (((ctx->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
796 /*
797 * This channel group was
798 * enabled, copy from received
799 * sample.
800 */
ea9cfed7 801 ctx->tmp_sample[i] = ctx->sample[j++];
6937bb75
BV
802 }
803 }
ea9cfed7
UH
804 memcpy(ctx->sample, ctx->tmp_sample, 4);
805 sr_dbg("ols: full sample 0x%.8x", *(int *)ctx->sample);
6937bb75
BV
806 }
807
a803c0db
BV
808 /* the OLS sends its sample buffer backwards.
809 * store it in reverse order here, so we can dump
810 * this on the session bus later.
811 */
ea9cfed7
UH
812 offset = (ctx->limit_samples - ctx->num_samples) * 4;
813 for (i = 0; i <= ctx->rle_count; i++) {
814 memcpy(ctx->raw_sample_buf + offset + (i * 4),
815 ctx->sample, 4);
baf1d714 816 }
ea9cfed7
UH
817 memset(ctx->sample, 0, 4);
818 ctx->num_bytes = 0;
819 ctx->rle_count = 0;
a1bb33af 820 }
43fc7885
UH
821 } else {
822 /*
823 * This is the main loop telling us a timeout was reached, or
824 * we've acquired all the samples we asked for -- we're done.
a803c0db 825 * Send the (properly-ordered) buffer to the frontend.
43fc7885 826 */
ea9cfed7 827 if (ctx->trigger_at != -1) {
a803c0db
BV
828 /* a trigger was set up, so we need to tell the frontend
829 * about it.
830 */
ea9cfed7 831 if (ctx->trigger_at > 0) {
a803c0db 832 /* there are pre-trigger samples, send those first */
5a2326a7 833 packet.type = SR_DF_LOGIC;
9c939c51 834 packet.payload = &logic;
ea9cfed7 835 logic.length = ctx->trigger_at * 4;
9c939c51 836 logic.unitsize = 4;
ea9cfed7
UH
837 logic.data = ctx->raw_sample_buf +
838 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 839 sr_session_send(cb_data, &packet);
a803c0db
BV
840 }
841
9c939c51 842 /* send the trigger */
5a2326a7 843 packet.type = SR_DF_TRIGGER;
1f9813eb 844 sr_session_send(cb_data, &packet);
a803c0db 845
9c939c51 846 /* send post-trigger samples */
5a2326a7 847 packet.type = SR_DF_LOGIC;
9c939c51 848 packet.payload = &logic;
ea9cfed7 849 logic.length = (ctx->num_samples * 4) - (ctx->trigger_at * 4);
9c939c51 850 logic.unitsize = 4;
ea9cfed7
UH
851 logic.data = ctx->raw_sample_buf + ctx->trigger_at * 4 +
852 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 853 sr_session_send(cb_data, &packet);
a803c0db 854 } else {
9c939c51 855 /* no trigger was used */
5a2326a7 856 packet.type = SR_DF_LOGIC;
9c939c51 857 packet.payload = &logic;
ea9cfed7 858 logic.length = ctx->num_samples * 4;
9c939c51 859 logic.unitsize = 4;
ea9cfed7
UH
860 logic.data = ctx->raw_sample_buf +
861 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 862 sr_session_send(cb_data, &packet);
a803c0db 863 }
ea9cfed7 864 g_free(ctx->raw_sample_buf);
a803c0db 865
06d64eb8 866 serial_flush(fd);
d02a535e 867 serial_close(fd);
5a2326a7 868 packet.type = SR_DF_END;
1f9813eb 869 sr_session_send(cb_data, &packet);
a1bb33af
UH
870 }
871
872 return TRUE;
873}
874
3cd3a20b 875static int hw_dev_acquisition_start(int dev_index, void *cb_data)
a1bb33af 876{
b9c735a2
UH
877 struct sr_datafeed_packet *packet;
878 struct sr_datafeed_header *header;
d68e2d1a 879 struct sr_dev_inst *sdi;
ea9cfed7 880 struct context *ctx;
a803c0db 881 uint32_t trigger_config[4];
a1bb33af 882 uint32_t data;
6937bb75
BV
883 uint16_t readcount, delaycount;
884 uint8_t changrp_mask;
22130421 885 int num_channels;
4fe9a6da 886 int i;
a1bb33af 887
bb7ef793 888 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
e46b8fb1 889 return SR_ERR;
c0a4b971 890
ea9cfed7 891 ctx = sdi->priv;
a1bb33af 892
5a2326a7 893 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 894 return SR_ERR;
a1bb33af 895
22130421
GM
896 /*
897 * Enable/disable channel groups in the flag register according to the
baf1d714 898 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
899 * to limit readcount.
900 */
901 changrp_mask = 0;
902 num_channels = 0;
903 for (i = 0; i < 4; i++) {
ea9cfed7 904 if (ctx->probe_mask & (0xff << (i * 8))) {
22130421
GM
905 changrp_mask |= (1 << i);
906 num_channels++;
907 }
908 }
909
baf1d714
UH
910 /*
911 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
912 * buffer.
913 */
ea9cfed7 914 readcount = MIN(ctx->max_samples / num_channels, ctx->limit_samples) / 4;
a803c0db
BV
915
916 memset(trigger_config, 0, 16);
ea9cfed7
UH
917 trigger_config[ctx->num_stages - 1] |= 0x08;
918 if (ctx->trigger_mask[0]) {
919 delaycount = readcount * (1 - ctx->capture_ratio / 100.0);
920 ctx->trigger_at = (readcount - delaycount) * 4 - ctx->num_stages;
a803c0db 921
ea9cfed7
UH
922 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
923 reverse32(ctx->trigger_mask[0])) != SR_OK)
e46b8fb1 924 return SR_ERR;
ea9cfed7
UH
925 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
926 reverse32(ctx->trigger_value[0])) != SR_OK)
e46b8fb1 927 return SR_ERR;
ea9cfed7 928 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
929 trigger_config[0]) != SR_OK)
930 return SR_ERR;
6937bb75 931
ea9cfed7
UH
932 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_1,
933 reverse32(ctx->trigger_mask[1])) != SR_OK)
e46b8fb1 934 return SR_ERR;
ea9cfed7
UH
935 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_1,
936 reverse32(ctx->trigger_value[1])) != SR_OK)
e46b8fb1 937 return SR_ERR;
ea9cfed7 938 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
939 trigger_config[1]) != SR_OK)
940 return SR_ERR;
6937bb75 941
ea9cfed7
UH
942 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_2,
943 reverse32(ctx->trigger_mask[2])) != SR_OK)
e46b8fb1 944 return SR_ERR;
ea9cfed7
UH
945 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_2,
946 reverse32(ctx->trigger_value[2])) != SR_OK)
e46b8fb1 947 return SR_ERR;
ea9cfed7 948 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
949 trigger_config[2]) != SR_OK)
950 return SR_ERR;
a803c0db 951
ea9cfed7
UH
952 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_3,
953 reverse32(ctx->trigger_mask[3])) != SR_OK)
e46b8fb1 954 return SR_ERR;
ea9cfed7
UH
955 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_3,
956 reverse32(ctx->trigger_value[3])) != SR_OK)
e46b8fb1 957 return SR_ERR;
ea9cfed7 958 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
959 trigger_config[3]) != SR_OK)
960 return SR_ERR;
6937bb75 961 } else {
ea9cfed7
UH
962 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
963 ctx->trigger_mask[0]) != SR_OK)
e46b8fb1 964 return SR_ERR;
ea9cfed7
UH
965 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
966 ctx->trigger_value[0]) != SR_OK)
e46b8fb1 967 return SR_ERR;
ea9cfed7 968 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
969 0x00000008) != SR_OK)
970 return SR_ERR;
a803c0db 971 delaycount = readcount;
6937bb75 972 }
a1bb33af 973
b08024a8 974 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
ea9cfed7
UH
975 "demux %s)", ctx->cur_samplerate, ctx->cur_samplerate_divider,
976 ctx->flag_reg & FLAG_DEMUX ? "on" : "off");
977 if (send_longcommand(ctx->serial->fd, CMD_SET_DIVIDER,
978 reverse32(ctx->cur_samplerate_divider)) != SR_OK)
4fe9a6da 979 return SR_ERR;
a1bb33af 980
43fc7885 981 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
982 data = ((readcount - 1) & 0xffff) << 16;
983 data |= (delaycount - 1) & 0xffff;
ea9cfed7 984 if (send_longcommand(ctx->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 985 return SR_ERR;
a1bb33af 986
43fc7885 987 /* The flag register wants them here, and 1 means "disable channel". */
ea9cfed7
UH
988 ctx->flag_reg |= ~(changrp_mask << 2) & 0x3c;
989 ctx->flag_reg |= FLAG_FILTER;
990 ctx->rle_count = 0;
991 data = (ctx->flag_reg << 24) | ((ctx->flag_reg << 8) & 0xff0000);
992 if (send_longcommand(ctx->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 993 return SR_ERR;
a1bb33af 994
43fc7885 995 /* Start acquisition on the device. */
ea9cfed7 996 if (send_shortcommand(ctx->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 997 return SR_ERR;
a1bb33af 998
ea9cfed7 999 sr_source_add(ctx->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1000 cb_data);
a1bb33af 1001
b53738ba
UH
1002 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1003 sr_err("ols: %s: packet malloc failed", __func__);
1004 return SR_ERR_MALLOC;
1005 }
1006
1007 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1008 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1009 g_free(packet);
b53738ba
UH
1010 return SR_ERR_MALLOC;
1011 }
1012
43fc7885 1013 /* Send header packet to the session bus. */
5a2326a7 1014 packet->type = SR_DF_HEADER;
43fc7885 1015 packet->payload = (unsigned char *)header;
a1bb33af
UH
1016 header->feed_version = 1;
1017 gettimeofday(&header->starttime, NULL);
ea9cfed7 1018 header->samplerate = ctx->cur_samplerate;
c2616fb9 1019 header->num_logic_probes = NUM_PROBES;
3cd3a20b 1020 sr_session_send(cb_data, packet);
c0a4b971 1021
a1bb33af
UH
1022 g_free(header);
1023 g_free(packet);
1024
e46b8fb1 1025 return SR_OK;
a1bb33af
UH
1026}
1027
3cd3a20b
UH
1028/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
1029static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
a1bb33af 1030{
b9c735a2 1031 struct sr_datafeed_packet packet;
a1bb33af 1032
17e1afcb 1033 /* Avoid compiler warnings. */
bb7ef793 1034 (void)dev_index;
afc8e4de 1035
5a2326a7 1036 packet.type = SR_DF_END;
3cd3a20b 1037 sr_session_send(cb_data, &packet);
3010f21c
UH
1038
1039 return SR_OK;
a1bb33af
UH
1040}
1041
c09f0b57 1042SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1043 .name = "ols",
1044 .longname = "Openbench Logic Sniffer",
1045 .api_version = 1,
1046 .init = hw_init,
1047 .cleanup = hw_cleanup,
e7eb703f
UH
1048 .dev_open = hw_dev_open,
1049 .dev_close = hw_dev_close,
5097b0d0 1050 .dev_info_get = hw_dev_info_get,
e7eb703f 1051 .dev_status_get = hw_dev_status_get,
ffedd0bf 1052 .hwcap_get_all = hw_hwcap_get_all,
a9a245b4 1053 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1054 .dev_acquisition_start = hw_dev_acquisition_start,
1055 .dev_acquisition_stop = hw_dev_acquisition_stop,
a1bb33af 1056};