[libsigrokdecode.git] / decoders / rtc8564 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
    return (b & 0x0f) + ((b >> 4) * 10)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'rtc8564'
    name = 'RTC-8564'
    longname = 'Epson RTC-8564 JE/NB'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['rtc8564']
    probes = []
    optional_probes = [
        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
    ]
    options = {}
    annotations = [
        ['reg-0x00', 'Register 0x00'],
        ['reg-0x01', 'Register 0x01'],
        ['reg-0x02', 'Register 0x02'],
        ['reg-0x03', 'Register 0x03'],
        ['reg-0x04', 'Register 0x04'],
        ['reg-0x05', 'Register 0x05'],
        ['reg-0x06', 'Register 0x06'],
        ['reg-0x07', 'Register 0x07'],
        ['reg-0x08', 'Register 0x08'],
        ['read', 'Read date/time'],
        ['write', 'Write date/time'],
        ['bits', 'Bits'],
    ]
    annotation_rows = (
        ('bits', 'Bits', (11,)),
        ('regs', 'Registers', tuple(range(0, 8 + 1))),
        ('date-time', 'Date/time', (9, 10)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.weekdays = -1
        self.months = -1
        self.years = -1

    def start(self):
        # self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def handle_reg_0x00(self, b): # Control register 1
        pass

    def handle_reg_0x01(self, b): # Control register 2
        ti_tp = 1 if (b & (1 << 4)) else 0
        af = 1 if (b & (1 << 3)) else 0
        tf = 1 if (b & (1 << 2)) else 0
        aie = 1 if (b & (1 << 1)) else 0
        tie = 1 if (b & (1 << 0)) else 0

        ann = ''

        s = 'repeated' if ti_tp else 'single-shot'
        ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
               'events\n' % (ti_tp, s)
        s = '' if af else 'no '
        ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
        s = '' if tf else 'no '
        ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
        s = 'enabled' if aie else 'prohibited'
        ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
               'occurs\n' % (aie, s)
        s = 'enabled' if tie else 'prohibited'
        ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
               'event occurs\n' % (tie, s)

        self.putx([1, [ann]])

    def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
        self.seconds = bcd2int(b & 0x7f)
        self.putx([2, ['Seconds: %d' % self.seconds]])
        vl = 1 if (b & (1 << 7)) else 0
        self.putx([11, ['Voltage low (VL) bit: %d' % vl]])

    def handle_reg_0x03(self, b): # Minutes
        self.minutes = bcd2int(b & 0x7f)
        self.putx([3, ['Minutes: %d' % self.minutes]])

    def handle_reg_0x04(self, b): # Hours
        self.hours = bcd2int(b & 0x3f)
        self.putx([4, ['Hours: %d' % self.hours]])

    def handle_reg_0x05(self, b): # Days
        self.days = bcd2int(b & 0x3f)
        self.putx([5, ['Days: %d' % self.days]])

    def handle_reg_0x06(self, b): # Weekdays
        self.weekdays = bcd2int(b & 0x07)
        self.putx([6, ['Weekdays: %d' % self.weekdays]])

    def handle_reg_0x07(self, b): # Months / century
        # TODO: Handle century bit.
        self.months = bcd2int(b & 0x1f)
        self.putx([7, ['Months: %d' % self.months]])

    def handle_reg_0x08(self, b): # Years
        self.years = bcd2int(b & 0xff)
        self.putx([8, ['Years: %d' % self.years]])

    def handle_reg_0x09(self, b): # Alarm, minute
        pass

    def handle_reg_0x0a(self, b): # Alarm, hour
        pass

    def handle_reg_0x0b(self, b): # Alarm, day
        pass

    def handle_reg_0x0c(self, b): # Alarm, weekday
        pass

    def handle_reg_0x0d(self, b): # CLKOUT output
        pass

    def handle_reg_0x0e(self, b): # Timer setting
        pass

    def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.block_start_sample = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [9, ['Write date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [10, ['Read date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
        else:
            raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
ed5f826a	1	##
50bd5d25	2	## This file is part of the libsigrokdecode project.
ed5f826a UH	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
ed5f826a UH	21	import sigrokdecode as srd
ed5f826a UH	22
ed5f826a UH	23	# Return the specified BCD number (max. 8 bits) as integer.
	24	def bcd2int(b):
	25	return (b & 0x0f) + ((b >> 4) * 10)
	26
	27	class Decoder(srd.Decoder):
	28	api_version = 1
	29	id = 'rtc8564'
	30	name = 'RTC-8564'
	31	longname = 'Epson RTC-8564 JE/NB'
a465436e	32	desc = 'Realtime clock module protocol.'
ed5f826a UH	33	license = 'gplv2+'
	34	inputs = ['i2c']
	35	outputs = ['rtc8564']
	36	probes = []
b77614bc	37	optional_probes = [
847e488b UH	38	{'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
	39	{'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
	40	{'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
ed5f826a UH	41	]
	42	options = {}
	43	annotations = [
a4289441 UH	44	['reg-0x00', 'Register 0x00'],
	45	['reg-0x01', 'Register 0x01'],
	46	['reg-0x02', 'Register 0x02'],
	47	['reg-0x03', 'Register 0x03'],
	48	['reg-0x04', 'Register 0x04'],
	49	['reg-0x05', 'Register 0x05'],
	50	['reg-0x06', 'Register 0x06'],
	51	['reg-0x07', 'Register 0x07'],
	52	['reg-0x08', 'Register 0x08'],
	53	['read', 'Read date/time'],
	54	['write', 'Write date/time'],
3161ab5a	55	['bits', 'Bits'],
ed5f826a	56	]
3161ab5a UH	57	annotation_rows = (
	58	('bits', 'Bits', (11,)),
	59	('regs', 'Registers', tuple(range(0, 8 + 1))),
	60	('date-time', 'Date/time', (9, 10)),
	61	)
ed5f826a UH	62
ed5f826a UH	63	def __init__(self, **kwargs):
2b716038	64	self.state = 'IDLE'
ed5f826a UH	65	self.hours = -1
	66	self.minutes = -1
	67	self.seconds = -1
	68	self.days = -1
3d190141	69	self.weekdays = -1
ed5f826a UH	70	self.months = -1
	71	self.years = -1
	72
8915b346	73	def start(self):
c515eed7	74	# self.out_python = self.register(srd.OUTPUT_PYTHON)
be465111	75	self.out_ann = self.register(srd.OUTPUT_ANN)
ed5f826a	76
ed5f826a UH	77	def putx(self, data):
	78	self.put(self.ss, self.es, self.out_ann, data)
	79
	80	def handle_reg_0x00(self, b): # Control register 1
	81	pass
	82
	83	def handle_reg_0x01(self, b): # Control register 2
	84	ti_tp = 1 if (b & (1 << 4)) else 0
	85	af = 1 if (b & (1 << 3)) else 0
	86	tf = 1 if (b & (1 << 2)) else 0
	87	aie = 1 if (b & (1 << 1)) else 0
	88	tie = 1 if (b & (1 << 0)) else 0
	89
	90	ann = ''
	91
	92	s = 'repeated' if ti_tp else 'single-shot'
	93	ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
	94	'events\n' % (ti_tp, s)
	95	s = '' if af else 'no '
	96	ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
	97	s = '' if tf else 'no '
	98	ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
	99	s = 'enabled' if aie else 'prohibited'
	100	ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
	101	'occurs\n' % (aie, s)
	102	s = 'enabled' if tie else 'prohibited'
	103	ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
	104	'event occurs\n' % (tie, s)
	105
a4289441	106	self.putx([1, [ann]])
ed5f826a UH	107
	108	def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
	109	self.seconds = bcd2int(b & 0x7f)
a4289441	110	self.putx([2, ['Seconds: %d' % self.seconds]])
ed5f826a	111	vl = 1 if (b & (1 << 7)) else 0
3161ab5a	112	self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
ed5f826a UH	113
	114	def handle_reg_0x03(self, b): # Minutes
	115	self.minutes = bcd2int(b & 0x7f)
a4289441	116	self.putx([3, ['Minutes: %d' % self.minutes]])
ed5f826a UH	117
	118	def handle_reg_0x04(self, b): # Hours
	119	self.hours = bcd2int(b & 0x3f)
a4289441	120	self.putx([4, ['Hours: %d' % self.hours]])
ed5f826a UH	121
	122	def handle_reg_0x05(self, b): # Days
	123	self.days = bcd2int(b & 0x3f)
a4289441	124	self.putx([5, ['Days: %d' % self.days]])
ed5f826a	125
3d190141 UH	126	def handle_reg_0x06(self, b): # Weekdays
	127	self.weekdays = bcd2int(b & 0x07)
	128	self.putx([6, ['Weekdays: %d' % self.weekdays]])
ed5f826a UH	129
	130	def handle_reg_0x07(self, b): # Months / century
	131	# TODO: Handle century bit.
	132	self.months = bcd2int(b & 0x1f)
a4289441	133	self.putx([7, ['Months: %d' % self.months]])
ed5f826a UH	134
	135	def handle_reg_0x08(self, b): # Years
	136	self.years = bcd2int(b & 0xff)
a4289441	137	self.putx([8, ['Years: %d' % self.years]])
ed5f826a UH	138
	139	def handle_reg_0x09(self, b): # Alarm, minute
	140	pass
	141
	142	def handle_reg_0x0a(self, b): # Alarm, hour
	143	pass
	144
	145	def handle_reg_0x0b(self, b): # Alarm, day
	146	pass
	147
	148	def handle_reg_0x0c(self, b): # Alarm, weekday
	149	pass
	150
	151	def handle_reg_0x0d(self, b): # CLKOUT output
	152	pass
	153
	154	def handle_reg_0x0e(self, b): # Timer setting
	155	pass
	156
	157	def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
	158	pass
	159
	160	def decode(self, ss, es, data):
1b75abfd	161	cmd, databyte = data
ed5f826a	162
00197484	163	# Store the start/end samples of this I²C packet.
ed5f826a UH	164	self.ss, self.es = ss, es
	165
	166	# State machine.
2b716038	167	if self.state == 'IDLE':
00197484	168	# Wait for an I²C START condition.
ed5f826a UH	169	if cmd != 'START':
ed5f826a UH	170	return
2b716038	171	self.state = 'GET SLAVE ADDR'
ed5f826a	172	self.block_start_sample = ss
2b716038	173	elif self.state == 'GET SLAVE ADDR':
ed5f826a UH	174	# Wait for an address write operation.
	175	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	176	if cmd != 'ADDRESS WRITE':
	177	return
2b716038 UH	178	self.state = 'GET REG ADDR'
2b716038 UH	179	elif self.state == 'GET REG ADDR':
ed5f826a UH	180	# Wait for a data write (master selects the slave register).
	181	if cmd != 'DATA WRITE':
	182	return
	183	self.reg = databyte
2b716038 UH	184	self.state = 'WRITE RTC REGS'
2b716038 UH	185	elif self.state == 'WRITE RTC REGS':
ed5f826a UH	186	# If we see a Repeated Start here, it's probably an RTC read.
ed5f826a UH	187	if cmd == 'START REPEAT':
2b716038	188	self.state = 'READ RTC REGS'
ed5f826a UH	189	return
	190	# Otherwise: Get data bytes until a STOP condition occurs.
	191	if cmd == 'DATA WRITE':
	192	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	193	handle_reg(databyte)
	194	self.reg += 1
	195	# TODO: Check for NACK!
	196	elif cmd == 'STOP':
	197	# TODO: Handle read/write of only parts of these items.
	198	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	199	self.years, self.hours, self.minutes, self.seconds)
	200	self.put(self.block_start_sample, es, self.out_ann,
a4289441	201	[9, ['Write date/time: %s' % d]])
2b716038	202	self.state = 'IDLE'
ed5f826a UH	203	else:
ed5f826a UH	204	pass # TODO
2b716038	205	elif self.state == 'READ RTC REGS':
ed5f826a UH	206	# Wait for an address read operation.
	207	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	208	if cmd == 'ADDRESS READ':
2b716038	209	self.state = 'READ RTC REGS2'
ed5f826a UH	210	return
ed5f826a UH	211	else:
e4f82268	212	pass # TODO
2b716038	213	elif self.state == 'READ RTC REGS2':
ed5f826a UH	214	if cmd == 'DATA READ':
	215	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	216	handle_reg(databyte)
	217	self.reg += 1
	218	# TODO: Check for NACK!
	219	elif cmd == 'STOP':
	220	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	221	self.years, self.hours, self.minutes, self.seconds)
	222	self.put(self.block_start_sample, es, self.out_ann,
a4289441	223	[10, ['Read date/time: %s' % d]])
2b716038	224	self.state = 'IDLE'
ed5f826a UH	225	else:
	226	pass # TODO?
	227	else:
0eeeb544	228	raise Exception('Invalid state: %s' % self.state)
ed5f826a	229