2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Return the specified BCD number (max. 8 bits) as integer.
25 return (b & 0x0f) + ((b >> 4) * 10)
27 class Decoder(srd.Decoder):
31 longname = 'Epson RTC-8564 JE/NB'
32 desc = 'Realtime clock module protocol.'
38 {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
39 {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
40 {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
44 ['reg-0x00', 'Register 0x00'],
45 ['reg-0x01', 'Register 0x01'],
46 ['reg-0x02', 'Register 0x02'],
47 ['reg-0x03', 'Register 0x03'],
48 ['reg-0x04', 'Register 0x04'],
49 ['reg-0x05', 'Register 0x05'],
50 ['reg-0x06', 'Register 0x06'],
51 ['reg-0x07', 'Register 0x07'],
52 ['reg-0x08', 'Register 0x08'],
53 ['read', 'Read date/time'],
54 ['write', 'Write date/time'],
58 ('bits', 'Bits', (11,)),
59 ('regs', 'Registers', tuple(range(0, 8 + 1))),
60 ('date-time', 'Date/time', (9, 10)),
63 def __init__(self, **kwargs):
74 # self.out_python = self.register(srd.OUTPUT_PYTHON)
75 self.out_ann = self.register(srd.OUTPUT_ANN)
78 self.put(self.ss, self.es, self.out_ann, data)
80 def handle_reg_0x00(self, b): # Control register 1
83 def handle_reg_0x01(self, b): # Control register 2
84 ti_tp = 1 if (b & (1 << 4)) else 0
85 af = 1 if (b & (1 << 3)) else 0
86 tf = 1 if (b & (1 << 2)) else 0
87 aie = 1 if (b & (1 << 1)) else 0
88 tie = 1 if (b & (1 << 0)) else 0
92 s = 'repeated' if ti_tp else 'single-shot'
93 ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
94 'events\n' % (ti_tp, s)
95 s = '' if af else 'no '
96 ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
97 s = '' if tf else 'no '
98 ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
99 s = 'enabled' if aie else 'prohibited'
100 ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
101 'occurs\n' % (aie, s)
102 s = 'enabled' if tie else 'prohibited'
103 ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
104 'event occurs\n' % (tie, s)
106 self.putx([1, [ann]])
108 def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
109 self.seconds = bcd2int(b & 0x7f)
110 self.putx([2, ['Seconds: %d' % self.seconds]])
111 vl = 1 if (b & (1 << 7)) else 0
112 self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
114 def handle_reg_0x03(self, b): # Minutes
115 self.minutes = bcd2int(b & 0x7f)
116 self.putx([3, ['Minutes: %d' % self.minutes]])
118 def handle_reg_0x04(self, b): # Hours
119 self.hours = bcd2int(b & 0x3f)
120 self.putx([4, ['Hours: %d' % self.hours]])
122 def handle_reg_0x05(self, b): # Days
123 self.days = bcd2int(b & 0x3f)
124 self.putx([5, ['Days: %d' % self.days]])
126 def handle_reg_0x06(self, b): # Weekdays
127 self.weekdays = bcd2int(b & 0x07)
128 self.putx([6, ['Weekdays: %d' % self.weekdays]])
130 def handle_reg_0x07(self, b): # Months / century
131 # TODO: Handle century bit.
132 self.months = bcd2int(b & 0x1f)
133 self.putx([7, ['Months: %d' % self.months]])
135 def handle_reg_0x08(self, b): # Years
136 self.years = bcd2int(b & 0xff)
137 self.putx([8, ['Years: %d' % self.years]])
139 def handle_reg_0x09(self, b): # Alarm, minute
142 def handle_reg_0x0a(self, b): # Alarm, hour
145 def handle_reg_0x0b(self, b): # Alarm, day
148 def handle_reg_0x0c(self, b): # Alarm, weekday
151 def handle_reg_0x0d(self, b): # CLKOUT output
154 def handle_reg_0x0e(self, b): # Timer setting
157 def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
160 def decode(self, ss, es, data):
163 # Store the start/end samples of this I²C packet.
164 self.ss, self.es = ss, es
167 if self.state == 'IDLE':
168 # Wait for an I²C START condition.
171 self.state = 'GET SLAVE ADDR'
172 self.block_start_sample = ss
173 elif self.state == 'GET SLAVE ADDR':
174 # Wait for an address write operation.
175 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
176 if cmd != 'ADDRESS WRITE':
178 self.state = 'GET REG ADDR'
179 elif self.state == 'GET REG ADDR':
180 # Wait for a data write (master selects the slave register).
181 if cmd != 'DATA WRITE':
184 self.state = 'WRITE RTC REGS'
185 elif self.state == 'WRITE RTC REGS':
186 # If we see a Repeated Start here, it's probably an RTC read.
187 if cmd == 'START REPEAT':
188 self.state = 'READ RTC REGS'
190 # Otherwise: Get data bytes until a STOP condition occurs.
191 if cmd == 'DATA WRITE':
192 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
195 # TODO: Check for NACK!
197 # TODO: Handle read/write of only parts of these items.
198 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
199 self.years, self.hours, self.minutes, self.seconds)
200 self.put(self.block_start_sample, es, self.out_ann,
201 [9, ['Write date/time: %s' % d]])
205 elif self.state == 'READ RTC REGS':
206 # Wait for an address read operation.
207 # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
208 if cmd == 'ADDRESS READ':
209 self.state = 'READ RTC REGS2'
213 elif self.state == 'READ RTC REGS2':
214 if cmd == 'DATA READ':
215 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
218 # TODO: Check for NACK!
220 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
221 self.years, self.hours, self.minutes, self.seconds)
222 self.put(self.block_start_sample, es, self.out_ann,
223 [10, ['Read date/time: %s' % d]])
228 raise Exception('Invalid state: %s' % self.state)