[libsigrokdecode.git] / decoders / onewire / onewire.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# 1-Wire protocol decoder

import sigrokdecode as srd

# Annotation feed formats
ANN_ASCII = 0
ANN_DEC = 1
ANN_HEX = 2
ANN_OCT = 3
ANN_BITS = 4

class Decoder(srd.Decoder):
    api_version = 1
    id = 'onewire'
    name = '1-Wire'
    longname = ''
    desc = '1-Wire bus and MicroLan'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['onewire']
    probes = [
        {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
    ]
    optional_probes = [
        {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
    ]
    options = {
        'overdrive': ['Overdrive', 0],
    }
    annotations = [
        ['ASCII', 'Data bytes as ASCII characters'],
        ['Decimal', 'Databytes as decimal, integer values'],
        ['Hex', 'Data bytes in hex format'],
        ['Octal', 'Data bytes as octal numbers'],
        ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
    ]

    def __init__(self, **kwargs):
        # Common variables
        self.samplenum = 0
        # Link layer variables
        self.lnk_state   = 'WAIT FOR FALLING EDGE'
        self.lnk_event   = 'NONE'
        self.lnk_fall    = 0
        self.lnk_present = 0
        self.lnk_bit     = 0
        self.lnk_cnt     = 0
        self.lnk_byte    = 0x00
        # Network layer variables
        self.net_mode    = 'WRITE'
        self.net_state   = 'WAIT FOR COMMAND'
        self.net_event   = 'NONE'
        self.net_cnt     = 0
        self.net_cmd     = 0x00
        # Transport layer variables
        self.trn_state   = 'WAIT FOR EVENT'
        self.trn_event   = 'NONE'

    def start(self, metadata):
        self.samplerate = metadata['samplerate']
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
        self.out_ann   = self.add(srd.OUTPUT_ANN  , 'onewire')

        # The width of the 1-Wire time base (30us) in number of samples.
        # TODO: optimize this value
        self.time_base = float(self.samplerate) * float(0.000030)
        print ("DEBUG: samplerate = %d, time_base = %d" % (self.samplerate, self.time_base))

    def report(self):
        pass

    def decode(self, ss, es, data):
        for (self.samplenum, (owr, pwr)) in data:
#            print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))

            # Data link layer

            # Clear events.
            self.lnk_event = "NONE"
            # State machine.
            if self.lnk_state == 'WAIT FOR FALLING EDGE':
                # The start of a cycle is a falling edge.
                if (owr == 0):
                    # Save the sample number for the falling edge.
                    self.lnk_fall = self.samplenum
                    # Go to waiting for sample time
                    self.lnk_state = 'WAIT FOR DATA SAMPLE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: NEGEDGE: ']])
            elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_fall == 1*self.time_base):
                    self.lnk_bit  = owr & 0x1
                    self.lnk_event = "DATA BIT"
                    if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: BIT: ' + str(self.lnk_bit)]])
            elif self.lnk_state == 'WAIT FOR RISING EDGE':
                # The end of a cycle is a rising edge.
                if (owr == 1):
                    # A reset cycle is longer than 8T.
                    if (self.samplenum - self.lnk_fall > 8*self.time_base):
                        # Save the sample number for the falling edge.
                        self.lnk_rise = self.samplenum
                        # Send a reset event to the next protocol layer.
                        self.lnk_event = "RESET"
                        self.lnk_state = "WAIT FOR PRESENCE DETECT"
                        self.put(self.lnk_fall, self.samplenum, self.out_proto,
                                 ['RESET'])
                        self.put(self.lnk_fall, self.samplenum, self.out_ann,
                                 [ANN_DEC, ['LNK: RESET: ']])
                        print ("DEBUG: RESET t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
                        # Reset the timer.
                        self.lnk_fall = self.samplenum
                    # Otherwise this is assumed to be a data bit.
                    else :
                        self.lnk_state = "WAIT FOR FALLING EDGE"
            elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
                    self.lnk_present = owr & 0x1
                    # Save the sample number for the falling edge.
                    if not (self.lnk_present) :  self.lnk_fall = self.samplenum
                    # create presence detect event
                    #self.lnk_event   = "PRESENCE DETECT"
                    if (self.lnk_present) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else                  :  self.lnk_state = 'WAIT FOR RISING EDGE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: PRESENCE: ' + str(self.lnk_present)]])
                    print ("DEBUG: PRESENCE=%d t0=%d t+=%d" % (self.lnk_present, self.lnk_fall, self.samplenum))
            else:
                raise Exception('Invalid lnk_state: %d' % self.lnk_state)

            # Link layer (byte sized units)
            
            # State machine.
            if (self.lnk_event == "RESET"):
                self.lnk_cnt  = 0
                self.lnk_byte = 0x00
            elif (self.lnk_event == "DATA BIT"):
                if (self.net_mode in ["WRITE", "READ"]):
                    self.lnk_cnt  = self.lnk_cnt + 1
                    self.lnk_byte = (self.lnk_byte << 1) | self.lnk_bit
                    if (self.lnk_cnt == 8):
                        print ("DEBUG: BYTE=0x%02x t0=%d t+=%d" % (self.lnk_byte, self.lnk_fall, self.samplenum))
                        self.lnk_event = "DATA BYTE"
                        self.lnk_cnt = 0
                        self.lnk_byte = 0x00
                elif (self.net_mode == "SEARCH"):
                    self.lnk_cnt  = self.lnk_cnt + 1
                    self.lnk_byte = (self.lnk_byte << 1) | self.lnk_bit
                    if (self.lnk_cnt == 8):
                        print ("DEBUG: BYTE=0x%02x t0=%d t+=%d" % (self.lnk_byte, self.lnk_fall, self.samplenum))
                        self.lnk_event = "DATA BYTE"
                        self.lnk_cnt = 0
                        self.lnk_byte = 0x00
                else:
                    raise Exception('Invalid net_mode: %s' % self.net_mode)
            elif not (self.lnk_event == "NONE"):
                raise Exception('Invalid lnk_event: %s' % self.lnk_event)

            # Network layer
            
            # Clear events.
            self.net_event = "RESET"
            # State machine.
            if (self.lnk_event == "RESET"):
                self.net_state = "WAIT FOR COMMAND"
                self.net_cnt = 0
            elif (self.lnk_event == "DATA BIT"):
                pass
            elif (self.lnk_event == "DATA BYTE"):
                if (self.net_state == "WAIT FOR COMMAND"):
                    self.net_cmd = self.lnk_byte
#                    self.put(self.lnk_fall, self.samplenum,
#                             self.out_proto, ['LNK: COMMAND', self.net_cmd])
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: COMMAND: 0x' + hex(self.net_cmd)]])
                    print ("DEBUG: CMD=0x%02x t0=%d t+=%d" % (self.net_cmd, self.lnk_fall, self.samplenum))
                    if   (self.net_cmd == 0x33):
                        # READ ROM
                        pass
                    elif (self.net_cmd == 0x0f):
                        # READ ROM
                        pass
                    elif (self.net_cmd == 0xcc):
                        # SKIP ROM
                        pass
                    elif (self.net_cmd == 0x55):
                        # MATCH ROM
                        pass
                    elif (self.net_cmd == 0xf0):
                        # SEARCH ROM
                        pass
                    elif (self.net_cmd == 0x3c):
                        # OVERDRIVE SKIP ROM
                        pass
                    elif (self.net_cmd == 0x69):
                        # OVERDRIVE MATCH ROM
                        pass
                    self.net_cnt = 0
                elif (self.net_state == "WAIT FOR ROM"):
                    #
                    pass
                else:
                    raise Exception('Invalid net_state: %d' % self.net_state)
            elif not (self.lnk_event == "NONE"):
                raise Exception('Invalid lnk_event: %s' % self.lnk_event)


#                    if (self.samplenum == self.lnk_start + 8*self.time_base):
#                        self.put(self.lnk_fall, self.samplenum - 1, self.out_proto, ['RESET'])
Commit	Line	Data
51990c45 IJ	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# 1-Wire protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Annotation feed formats
	26	ANN_ASCII = 0
	27	ANN_DEC = 1
	28	ANN_HEX = 2
	29	ANN_OCT = 3
	30	ANN_BITS = 4
	31
	32	class Decoder(srd.Decoder):
	33	api_version = 1
	34	id = 'onewire'
	35	name = '1-Wire'
	36	longname = ''
	37	desc = '1-Wire bus and MicroLan'
	38	license = 'gplv2+'
	39	inputs = ['logic']
	40	outputs = ['onewire']
	41	probes = [
	42	{'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
	43	]
	44	optional_probes = [
	45	{'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
	46	]
	47	options = {
	48	'overdrive': ['Overdrive', 0],
	49	}
	50	annotations = [
	51	['ASCII', 'Data bytes as ASCII characters'],
	52	['Decimal', 'Databytes as decimal, integer values'],
	53	['Hex', 'Data bytes in hex format'],
	54	['Octal', 'Data bytes as octal numbers'],
	55	['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
	56	]
	57
51990c45 IJ	58	def __init__(self, **kwargs):
	59	# Common variables
	60	self.samplenum = 0
	61	# Link layer variables
af623785 IJ	62	self.lnk_state = 'WAIT FOR FALLING EDGE'
	63	self.lnk_event = 'NONE'
	64	self.lnk_fall = 0
	65	self.lnk_present = 0
	66	self.lnk_bit = 0
cf0f9df0 IJ	67	self.lnk_cnt = 0
cf0f9df0 IJ	68	self.lnk_byte = 0x00
51990c45	69	# Network layer variables
cf0f9df0	70	self.net_mode = 'WRITE'
af623785 IJ	71	self.net_state = 'WAIT FOR COMMAND'
	72	self.net_event = 'NONE'
	73	self.net_cnt = 0
cf0f9df0	74	self.net_cmd = 0x00
51990c45	75	# Transport layer variables
af623785 IJ	76	self.trn_state = 'WAIT FOR EVENT'
af623785 IJ	77	self.trn_event = 'NONE'
51990c45 IJ	78
	79	def start(self, metadata):
	80	self.samplerate = metadata['samplerate']
	81	self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
4fe36ec3	82	self.out_ann = self.add(srd.OUTPUT_ANN , 'onewire')
51990c45 IJ	83
	84	# The width of the 1-Wire time base (30us) in number of samples.
	85	# TODO: optimize this value
af623785 IJ	86	self.time_base = float(self.samplerate) * float(0.000030)
af623785 IJ	87	print ("DEBUG: samplerate = %d, time_base = %d" % (self.samplerate, self.time_base))
51990c45 IJ	88
	89	def report(self):
	90	pass
	91
51990c45	92	def decode(self, ss, es, data):
af623785 IJ	93	for (self.samplenum, (owr, pwr)) in data:
af623785 IJ	94	# print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))
51990c45	95
51990c45	96	# Data link layer
39a0219a IJ	97
39a0219a IJ	98	# Clear events.
af623785	99	self.lnk_event = "NONE"
39a0219a	100	# State machine.
51990c45 IJ	101	if self.lnk_state == 'WAIT FOR FALLING EDGE':
51990c45 IJ	102	# The start of a cycle is a falling edge.
39a0219a IJ	103	if (owr == 0):
	104	# Save the sample number for the falling edge.
	105	self.lnk_fall = self.samplenum
51990c45	106	# Go to waiting for sample time
39a0219a	107	self.lnk_state = 'WAIT FOR DATA SAMPLE'
af623785 IJ	108	self.put(self.lnk_fall, self.samplenum, self.out_ann,
af623785 IJ	109	[ANN_DEC, ['LNK: NEGEDGE: ']])
39a0219a	110	elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
51990c45	111	# Data should be sample one 'time unit' after a falling edge
39a0219a	112	if (self.samplenum - self.lnk_fall == 1*self.time_base):
51990c45	113	self.lnk_bit = owr & 0x1
39a0219a IJ	114	self.lnk_event = "DATA BIT"
	115	if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
	116	else : self.lnk_state = 'WAIT FOR RISING EDGE'
af623785 IJ	117	self.put(self.lnk_fall, self.samplenum, self.out_ann,
af623785 IJ	118	[ANN_DEC, ['LNK: BIT: ' + str(self.lnk_bit)]])
51990c45 IJ	119	elif self.lnk_state == 'WAIT FOR RISING EDGE':
51990c45 IJ	120	# The end of a cycle is a rising edge.
39a0219a	121	if (owr == 1):
af623785	122	# A reset cycle is longer than 8T.
39a0219a IJ	123	if (self.samplenum - self.lnk_fall > 8*self.time_base):
	124	# Save the sample number for the falling edge.
	125	self.lnk_rise = self.samplenum
af623785	126	# Send a reset event to the next protocol layer.
39a0219a IJ	127	self.lnk_event = "RESET"
39a0219a IJ	128	self.lnk_state = "WAIT FOR PRESENCE DETECT"
af623785 IJ	129	self.put(self.lnk_fall, self.samplenum, self.out_proto,
	130	['RESET'])
	131	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	132	[ANN_DEC, ['LNK: RESET: ']])
	133	print ("DEBUG: RESET t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
	134	# Reset the timer.
	135	self.lnk_fall = self.samplenum
	136	# Otherwise this is assumed to be a data bit.
	137	else :
	138	self.lnk_state = "WAIT FOR FALLING EDGE"
39a0219a IJ	139	elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
	140	# Data should be sample one 'time unit' after a falling edge
	141	if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
af623785	142	self.lnk_present = owr & 0x1
cf0f9df0 IJ	143	# Save the sample number for the falling edge.
	144	if not (self.lnk_present) : self.lnk_fall = self.samplenum
	145	# create presence detect event
af623785	146	#self.lnk_event = "PRESENCE DETECT"
cf0f9df0 IJ	147	if (self.lnk_present) : self.lnk_state = 'WAIT FOR FALLING EDGE'
cf0f9df0 IJ	148	else : self.lnk_state = 'WAIT FOR RISING EDGE'
af623785 IJ	149	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	150	[ANN_DEC, ['LNK: PRESENCE: ' + str(self.lnk_present)]])
	151	print ("DEBUG: PRESENCE=%d t0=%d t+=%d" % (self.lnk_present, self.lnk_fall, self.samplenum))
39a0219a	152	else:
0631e33d	153	raise Exception('Invalid lnk_state: %d' % self.lnk_state)
39a0219a	154
cf0f9df0 IJ	155	# Link layer (byte sized units)
	156
	157	# State machine.
	158	if (self.lnk_event == "RESET"):
	159	self.lnk_cnt = 0
	160	self.lnk_byte = 0x00
	161	elif (self.lnk_event == "DATA BIT"):
	162	if (self.net_mode in ["WRITE", "READ"]):
	163	self.lnk_cnt = self.lnk_cnt + 1
	164	self.lnk_byte = (self.lnk_byte << 1) \| self.lnk_bit
	165	if (self.lnk_cnt == 8):
	166	print ("DEBUG: BYTE=0x%02x t0=%d t+=%d" % (self.lnk_byte, self.lnk_fall, self.samplenum))
	167	self.lnk_event = "DATA BYTE"
	168	self.lnk_cnt = 0
	169	self.lnk_byte = 0x00
	170	elif (self.net_mode == "SEARCH"):
	171	self.lnk_cnt = self.lnk_cnt + 1
	172	self.lnk_byte = (self.lnk_byte << 1) \| self.lnk_bit
	173	if (self.lnk_cnt == 8):
	174	print ("DEBUG: BYTE=0x%02x t0=%d t+=%d" % (self.lnk_byte, self.lnk_fall, self.samplenum))
	175	self.lnk_event = "DATA BYTE"
	176	self.lnk_cnt = 0
	177	self.lnk_byte = 0x00
	178	else:
	179	raise Exception('Invalid net_mode: %s' % self.net_mode)
	180	elif not (self.lnk_event == "NONE"):
	181	raise Exception('Invalid lnk_event: %s' % self.lnk_event)
	182
39a0219a IJ	183	# Network layer
	184
	185	# Clear events.
	186	self.net_event = "RESET"
	187	# State machine.
4fe36ec3	188	if (self.lnk_event == "RESET"):
39a0219a IJ	189	self.net_state = "WAIT FOR COMMAND"
39a0219a IJ	190	self.net_cnt = 0
4fe36ec3	191	elif (self.lnk_event == "DATA BIT"):
cf0f9df0 IJ	192	pass
cf0f9df0 IJ	193	elif (self.lnk_event == "DATA BYTE"):
4fe36ec3	194	if (self.net_state == "WAIT FOR COMMAND"):
cf0f9df0 IJ	195	self.net_cmd = self.lnk_byte
	196	# self.put(self.lnk_fall, self.samplenum,
	197	# self.out_proto, ['LNK: COMMAND', self.net_cmd])
	198	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	199	[ANN_DEC, ['LNK: COMMAND: 0x' + hex(self.net_cmd)]])
	200	print ("DEBUG: CMD=0x%02x t0=%d t+=%d" % (self.net_cmd, self.lnk_fall, self.samplenum))
	201	if (self.net_cmd == 0x33):
	202	# READ ROM
	203	pass
	204	elif (self.net_cmd == 0x0f):
	205	# READ ROM
	206	pass
	207	elif (self.net_cmd == 0xcc):
	208	# SKIP ROM
	209	pass
	210	elif (self.net_cmd == 0x55):
	211	# MATCH ROM
	212	pass
	213	elif (self.net_cmd == 0xf0):
	214	# SEARCH ROM
	215	pass
	216	elif (self.net_cmd == 0x3c):
	217	# OVERDRIVE SKIP ROM
	218	pass
	219	elif (self.net_cmd == 0x69):
	220	# OVERDRIVE MATCH ROM
	221	pass
	222	self.net_cnt = 0
af623785	223	elif (self.net_state == "WAIT FOR ROM"):
39a0219a	224	#
cf0f9df0	225	pass
39a0219a	226	else:
0631e33d	227	raise Exception('Invalid net_state: %d' % self.net_state)
39a0219a	228	elif not (self.lnk_event == "NONE"):
af623785	229	raise Exception('Invalid lnk_event: %s' % self.lnk_event)
51990c45	230
51990c45	231
4fe36ec3	232	# if (self.samplenum == self.lnk_start + 8*self.time_base):
af623785	233	# self.put(self.lnk_fall, self.samplenum - 1, self.out_proto, ['RESET'])