[libsigrokdecode.git] / decoders / onewire / onewire.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# 1-Wire protocol decoder

import sigrokdecode as srd

# Annotation feed formats
ANN_ASCII = 0
ANN_DEC = 1
ANN_HEX = 2
ANN_OCT = 3
ANN_BITS = 4

class Decoder(srd.Decoder):
    api_version = 1
    id = 'onewire'
    name = '1-Wire'
    longname = ''
    desc = '1-Wire bus and MicroLan'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['onewire']
    probes = [
        {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
    ]
    optional_probes = [
        {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
    ]
    options = {
        'overdrive': ['Overdrive', 0],
    }
    annotations = [
        ['ASCII', 'Data bytes as ASCII characters'],
        ['Decimal', 'Databytes as decimal, integer values'],
        ['Hex', 'Data bytes in hex format'],
        ['Octal', 'Data bytes as octal numbers'],
        ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
    ]

    def __init__(self, **kwargs):
        # Common variables
        self.samplenum = 0
        # Link layer variables
        self.lnk_state   = 'WAIT FOR FALLING EDGE'
        self.lnk_event   = 'NONE'
        self.lnk_fall    = 0
        self.lnk_present = 0
        self.lnk_bit     = 0
        # Network layer variables
        self.net_state   = 'WAIT FOR COMMAND'
        self.net_event   = 'NONE'
        self.net_cnt     = 0
        self.net_cmd     = 0
        # Transport layer variables
        self.trn_state   = 'WAIT FOR EVENT'
        self.trn_event   = 'NONE'

    def start(self, metadata):
        self.samplerate = metadata['samplerate']
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
        self.out_ann   = self.add(srd.OUTPUT_ANN  , 'onewire')

        # The width of the 1-Wire time base (30us) in number of samples.
        # TODO: optimize this value
        self.time_base = float(self.samplerate) * float(0.000030)
        print ("DEBUG: samplerate = %d, time_base = %d" % (self.samplerate, self.time_base))

    def report(self):
        pass

    def decode(self, ss, es, data):
        for (self.samplenum, (owr, pwr)) in data:
#            print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))

            # Data link layer

            # Clear events.
            self.lnk_event = "NONE"
            # State machine.
            if self.lnk_state == 'WAIT FOR FALLING EDGE':
                # The start of a cycle is a falling edge.
                if (owr == 0):
                    # Save the sample number for the falling edge.
                    self.lnk_fall = self.samplenum
                    # Go to waiting for sample time
                    self.lnk_state = 'WAIT FOR DATA SAMPLE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: NEGEDGE: ']])
                    print ("DEBUG: NEGEDGE t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
            elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_fall == 1*self.time_base):
                    self.lnk_bit  = owr & 0x1
                    self.lnk_event = "DATA BIT"
                    if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: BIT: ' + str(self.lnk_bit)]])
                    print ("DEBUG: BIT=%d t0=%d t+=%d" % (self.lnk_bit, self.lnk_fall, self.samplenum))
            elif self.lnk_state == 'WAIT FOR RISING EDGE':
                # The end of a cycle is a rising edge.
                if (owr == 1):
                    # A reset cycle is longer than 8T.
                    if (self.samplenum - self.lnk_fall > 8*self.time_base):
                        # Save the sample number for the falling edge.
                        self.lnk_rise = self.samplenum
                        # Send a reset event to the next protocol layer.
                        self.lnk_event = "RESET"
                        self.lnk_state = "WAIT FOR PRESENCE DETECT"
                        self.put(self.lnk_fall, self.samplenum, self.out_proto,
                                 ['RESET'])
                        self.put(self.lnk_fall, self.samplenum, self.out_ann,
                                 [ANN_DEC, ['LNK: RESET: ']])
                        print ("DEBUG: RESET t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
                        # Reset the timer.
                        self.lnk_fall = self.samplenum
                    # Otherwise this is assumed to be a data bit.
                    else :
                        self.lnk_state = "WAIT FOR FALLING EDGE"
            elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
                # Data should be sample one 'time unit' after a falling edge
                if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
                    self.lnk_present = owr & 0x1
                    #self.lnk_event   = "PRESENCE DETECT"
                    if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                    else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
                    self.put(self.lnk_fall, self.samplenum, self.out_ann,
                             [ANN_DEC, ['LNK: PRESENCE: ' + str(self.lnk_present)]])
                    print ("DEBUG: PRESENCE=%d t0=%d t+=%d" % (self.lnk_present, self.lnk_fall, self.samplenum))
            else:
                raise Exception('Invalid lnk_state: %d' % self.lnk_state)

            # Network layer
            
            # Clear events.
            self.net_event = "RESET"
            # State machine.
            if (self.lnk_event == "RESET"):
                self.net_state = "WAIT FOR COMMAND"
                self.net_cnt = 0
                self.net_cmd = 0
            elif (self.lnk_event == "DATA BIT"):
                if (self.net_state == "WAIT FOR COMMAND"):
                    self.net_cnt = self.net_cnt + 1
                    self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
                    if (self.net_cnt == 8):
                        self.put(self.lnk_fall, self.samplenum,
                                 self.out_proto, ['LNK: COMMAND', self.net_cmd])
                        self.put(self.lnk_fall, self.samplenum, self.out_ann,
                                 [ANN_DEC, ['LNK: COMMAND: ' + self.net_cmd]])
                        if   (self.net_cmd == 0x33):
                            # READ ROM
                            break
                        elif (self.net_cmd == 0x0f):
                            # READ ROM
                            break
                        elif (self.net_cmd == 0xcc):
                            # SKIP ROM
                            break
                        elif (self.net_cmd == 0x55):
                            # MATCH ROM
                            break
                        elif (self.net_cmd == 0xf0):
                            # SEARCH ROM
                            break
                        elif (self.net_cmd == 0x3c):
                            # OVERDRIVE SKIP ROM
                            break
                        elif (self.net_cmd == 0x69):
                            # OVERDRIVE MATCH ROM
                            break
                        self.net_cnt = 0
                elif (self.net_state == "WAIT FOR ROM"):
                    #
                    break
                else:
                    raise Exception('Invalid net_state: %d' % self.net_state)
            elif not (self.lnk_event == "NONE"):
                raise Exception('Invalid lnk_event: %s' % self.lnk_event)


#                    if (self.samplenum == self.lnk_start + 8*self.time_base):
#                        self.put(self.lnk_fall, self.samplenum - 1, self.out_proto, ['RESET'])
Commit	Line	Data
51990c45 IJ	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# 1-Wire protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# Annotation feed formats
	26	ANN_ASCII = 0
	27	ANN_DEC = 1
	28	ANN_HEX = 2
	29	ANN_OCT = 3
	30	ANN_BITS = 4
	31
	32	class Decoder(srd.Decoder):
	33	api_version = 1
	34	id = 'onewire'
	35	name = '1-Wire'
	36	longname = ''
	37	desc = '1-Wire bus and MicroLan'
	38	license = 'gplv2+'
	39	inputs = ['logic']
	40	outputs = ['onewire']
	41	probes = [
	42	{'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
	43	]
	44	optional_probes = [
	45	{'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
	46	]
	47	options = {
	48	'overdrive': ['Overdrive', 0],
	49	}
	50	annotations = [
	51	['ASCII', 'Data bytes as ASCII characters'],
	52	['Decimal', 'Databytes as decimal, integer values'],
	53	['Hex', 'Data bytes in hex format'],
	54	['Octal', 'Data bytes as octal numbers'],
	55	['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
	56	]
	57
51990c45 IJ	58	def __init__(self, **kwargs):
	59	# Common variables
	60	self.samplenum = 0
	61	# Link layer variables
af623785 IJ	62	self.lnk_state = 'WAIT FOR FALLING EDGE'
	63	self.lnk_event = 'NONE'
	64	self.lnk_fall = 0
	65	self.lnk_present = 0
	66	self.lnk_bit = 0
51990c45	67	# Network layer variables
af623785 IJ	68	self.net_state = 'WAIT FOR COMMAND'
	69	self.net_event = 'NONE'
	70	self.net_cnt = 0
	71	self.net_cmd = 0
51990c45	72	# Transport layer variables
af623785 IJ	73	self.trn_state = 'WAIT FOR EVENT'
af623785 IJ	74	self.trn_event = 'NONE'
51990c45 IJ	75
	76	def start(self, metadata):
	77	self.samplerate = metadata['samplerate']
	78	self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
4fe36ec3	79	self.out_ann = self.add(srd.OUTPUT_ANN , 'onewire')
51990c45 IJ	80
	81	# The width of the 1-Wire time base (30us) in number of samples.
	82	# TODO: optimize this value
af623785 IJ	83	self.time_base = float(self.samplerate) * float(0.000030)
af623785 IJ	84	print ("DEBUG: samplerate = %d, time_base = %d" % (self.samplerate, self.time_base))
51990c45 IJ	85
	86	def report(self):
	87	pass
	88
51990c45	89	def decode(self, ss, es, data):
af623785 IJ	90	for (self.samplenum, (owr, pwr)) in data:
af623785 IJ	91	# print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))
51990c45	92
51990c45	93	# Data link layer
39a0219a IJ	94
39a0219a IJ	95	# Clear events.
af623785	96	self.lnk_event = "NONE"
39a0219a	97	# State machine.
51990c45 IJ	98	if self.lnk_state == 'WAIT FOR FALLING EDGE':
51990c45 IJ	99	# The start of a cycle is a falling edge.
39a0219a IJ	100	if (owr == 0):
	101	# Save the sample number for the falling edge.
	102	self.lnk_fall = self.samplenum
51990c45	103	# Go to waiting for sample time
39a0219a	104	self.lnk_state = 'WAIT FOR DATA SAMPLE'
af623785 IJ	105	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	106	[ANN_DEC, ['LNK: NEGEDGE: ']])
	107	print ("DEBUG: NEGEDGE t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
39a0219a	108	elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
51990c45	109	# Data should be sample one 'time unit' after a falling edge
39a0219a	110	if (self.samplenum - self.lnk_fall == 1*self.time_base):
51990c45	111	self.lnk_bit = owr & 0x1
39a0219a IJ	112	self.lnk_event = "DATA BIT"
	113	if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
	114	else : self.lnk_state = 'WAIT FOR RISING EDGE'
af623785 IJ	115	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	116	[ANN_DEC, ['LNK: BIT: ' + str(self.lnk_bit)]])
	117	print ("DEBUG: BIT=%d t0=%d t+=%d" % (self.lnk_bit, self.lnk_fall, self.samplenum))
51990c45 IJ	118	elif self.lnk_state == 'WAIT FOR RISING EDGE':
51990c45 IJ	119	# The end of a cycle is a rising edge.
39a0219a	120	if (owr == 1):
af623785	121	# A reset cycle is longer than 8T.
39a0219a IJ	122	if (self.samplenum - self.lnk_fall > 8*self.time_base):
	123	# Save the sample number for the falling edge.
	124	self.lnk_rise = self.samplenum
af623785	125	# Send a reset event to the next protocol layer.
39a0219a IJ	126	self.lnk_event = "RESET"
39a0219a IJ	127	self.lnk_state = "WAIT FOR PRESENCE DETECT"
af623785 IJ	128	self.put(self.lnk_fall, self.samplenum, self.out_proto,
	129	['RESET'])
	130	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	131	[ANN_DEC, ['LNK: RESET: ']])
	132	print ("DEBUG: RESET t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
	133	# Reset the timer.
	134	self.lnk_fall = self.samplenum
	135	# Otherwise this is assumed to be a data bit.
	136	else :
	137	self.lnk_state = "WAIT FOR FALLING EDGE"
39a0219a IJ	138	elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
	139	# Data should be sample one 'time unit' after a falling edge
	140	if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
af623785 IJ	141	self.lnk_present = owr & 0x1
af623785 IJ	142	#self.lnk_event = "PRESENCE DETECT"
39a0219a IJ	143	if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
39a0219a IJ	144	else : self.lnk_state = 'WAIT FOR RISING EDGE'
af623785 IJ	145	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	146	[ANN_DEC, ['LNK: PRESENCE: ' + str(self.lnk_present)]])
	147	print ("DEBUG: PRESENCE=%d t0=%d t+=%d" % (self.lnk_present, self.lnk_fall, self.samplenum))
39a0219a	148	else:
0631e33d	149	raise Exception('Invalid lnk_state: %d' % self.lnk_state)
39a0219a IJ	150
	151	# Network layer
	152
	153	# Clear events.
	154	self.net_event = "RESET"
	155	# State machine.
4fe36ec3	156	if (self.lnk_event == "RESET"):
39a0219a IJ	157	self.net_state = "WAIT FOR COMMAND"
	158	self.net_cnt = 0
	159	self.net_cmd = 0
4fe36ec3 IJ	160	elif (self.lnk_event == "DATA BIT"):
4fe36ec3 IJ	161	if (self.net_state == "WAIT FOR COMMAND"):
39a0219a IJ	162	self.net_cnt = self.net_cnt + 1
39a0219a IJ	163	self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
af623785 IJ	164	if (self.net_cnt == 8):
	165	self.put(self.lnk_fall, self.samplenum,
	166	self.out_proto, ['LNK: COMMAND', self.net_cmd])
	167	self.put(self.lnk_fall, self.samplenum, self.out_ann,
	168	[ANN_DEC, ['LNK: COMMAND: ' + self.net_cmd]])
4fe36ec3	169	if (self.net_cmd == 0x33):
39a0219a	170	# READ ROM
4fe36ec3 IJ	171	break
4fe36ec3 IJ	172	elif (self.net_cmd == 0x0f):
39a0219a	173	# READ ROM
4fe36ec3 IJ	174	break
4fe36ec3 IJ	175	elif (self.net_cmd == 0xcc):
39a0219a	176	# SKIP ROM
4fe36ec3 IJ	177	break
4fe36ec3 IJ	178	elif (self.net_cmd == 0x55):
39a0219a	179	# MATCH ROM
4fe36ec3 IJ	180	break
4fe36ec3 IJ	181	elif (self.net_cmd == 0xf0):
39a0219a	182	# SEARCH ROM
4fe36ec3 IJ	183	break
4fe36ec3 IJ	184	elif (self.net_cmd == 0x3c):
39a0219a	185	# OVERDRIVE SKIP ROM
4fe36ec3 IJ	186	break
4fe36ec3 IJ	187	elif (self.net_cmd == 0x69):
39a0219a	188	# OVERDRIVE MATCH ROM
4fe36ec3	189	break
af623785 IJ	190	self.net_cnt = 0
af623785 IJ	191	elif (self.net_state == "WAIT FOR ROM"):
39a0219a	192	#
4fe36ec3	193	break
39a0219a	194	else:
0631e33d	195	raise Exception('Invalid net_state: %d' % self.net_state)
39a0219a	196	elif not (self.lnk_event == "NONE"):
af623785	197	raise Exception('Invalid lnk_event: %s' % self.lnk_event)
51990c45	198
51990c45	199
4fe36ec3	200	# if (self.samplenum == self.lnk_start + 8*self.time_base):
af623785	201	# self.put(self.lnk_fall, self.samplenum - 1, self.out_proto, ['RESET'])