[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE()

#define SET_COUPLING(x)

#define SET_CALIBRATION_PULSE(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

#define TIMER2_VAL 500

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -TIMER2_VAL & 0xff;
	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE()
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x)
	30
	31	#define SET_CALIBRATION_PULSE(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7
	35
65b34f7e UH	36	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	37	#define LED_GREEN() PC0 = 1; PC1 = 0;
	38	#define LED_RED() PC0 = 0; PC1 = 1;
	39
2c57c00b UH	40	#define TIMER2_VAL 500
2c57c00b UH	41
e1c5ba21 UH	42	/* CTLx pin index (IFCLK, ADC clock input). */
	43	#define CTL_BIT 2
	44
	45	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	46	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	47
cc789c14	48	/* Change to support as many interfaces as you need. */
0ab4ea5d	49	static BYTE altiface = 0;
189db3d4	50
0ab4ea5d	51	static volatile WORD ledcounter = 0;
189db3d4	52
0ab4ea5d UH	53	static volatile __bit dosud = FALSE;
0ab4ea5d UH	54	static volatile __bit dosuspend = FALSE;
cc789c14 UH	55
	56	extern __code BYTE highspd_dscr;
	57	extern __code BYTE fullspd_dscr;
189db3d4	58
cc789c14 UH	59	void resume_isr(void) __interrupt RESUME_ISR
	60	{
	61	CLEAR_RESUME();
189db3d4	62	}
cc789c14 UH	63
	64	void sudav_isr(void) __interrupt SUDAV_ISR
	65	{
	66	dosud = TRUE;
	67	CLEAR_SUDAV();
189db3d4	68	}
cc789c14 UH	69
	70	void usbreset_isr(void) __interrupt USBRESET_ISR
	71	{
	72	handle_hispeed(FALSE);
	73	CLEAR_USBRESET();
189db3d4	74	}
cc789c14 UH	75
	76	void hispeed_isr(void) __interrupt HISPEED_ISR
	77	{
	78	handle_hispeed(TRUE);
	79	CLEAR_HISPEED();
189db3d4 UH	80	}
189db3d4 UH	81
cc789c14 UH	82	void suspend_isr(void) __interrupt SUSPEND_ISR
	83	{
	84	dosuspend = TRUE;
	85	CLEAR_SUSPEND();
189db3d4 UH	86	}
189db3d4 UH	87
cc789c14 UH	88	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	89	{
e583c3fc	90	TOGGLE_CALIBRATION_PIN();
3968bbfb	91
65b34f7e UH	92	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	93	LED_CLEAR();
3968bbfb	94
cc789c14	95	TF2 = 0;
189db3d4	96	}
189db3d4	97
cc789c14 UH	98	/*
cc789c14 UH	99	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	100	* For channel 0 we want to set bits 5, 6 & 7
	101	* For channel 1 we want to set bits 2, 3 & 4
	102	*
cc789c14 UH	103	* We convert the input values that are strange due to original
	104	* firmware code into the value of the three bits as follows:
	105	*
189db3d4 UH	106	* val -> bits
	107	* 1 -> 010b
	108	* 2 -> 001b
	109	* 5 -> 000b
	110	* 10 -> 011b
	111	*
cc789c14 UH	112	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	113	* in the serial selector chip.
189db3d4 UH	114	*
	115	* The multiplication of the converted value by 0x24 sets the relevant bits in
	116	* both channels and then we mask it out to only affect the channel currently
	117	* requested.
	118	*/
0ab4ea5d	119	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	120	{
cc789c14 UH	121	BYTE bits, mask;
	122
	123	switch (val) {
	124	case 1:
	125	bits = 0x24 * 2;
	126	break;
	127	case 2:
	128	bits = 0x24 * 1;
	129	break;
	130	case 5:
	131	bits = 0x24 * 0;
	132	break;
	133	case 10:
	134	bits = 0x24 * 3;
	135	break;
	136	default:
	137	return FALSE;
	138	}
	139
	140	mask = (channel) ? 0xe0 : 0x1c;
	141	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	142
cc789c14	143	return TRUE;
189db3d4 UH	144	}
189db3d4 UH	145
297fb13a UH	146	/**
	147	* Each LSB in the nibble of the byte controls the coupling per channel.
	148	*
	149	* Setting PE3 disables AC coupling capacitor on CH0.
	150	* Setting PE0 disables AC coupling capacitor on CH1.
	151	*/
	152	static void set_coupling(BYTE coupling_cfg)
	153	{
	154	if (coupling_cfg & 0x01)
	155	IOE \|= 0x08;
	156	else
	157	IOE &= ~0x08;
	158
	159	if (coupling_cfg & 0x10)
	160	IOE \|= 0x01;
	161	else
	162	IOE &= ~0x01;
	163	}
	164
0ab4ea5d	165	static BOOL set_numchannels(BYTE numchannels)
189db3d4	166	{
cc789c14 UH	167	if (numchannels == 1 \|\| numchannels == 2) {
	168	BYTE fifocfg = 7 + numchannels;
	169	EP2FIFOCFG = fifocfg;
	170	EP6FIFOCFG = fifocfg;
	171	return TRUE;
	172	}
	173
	174	return FALSE;
189db3d4 UH	175	}
189db3d4 UH	176
0ab4ea5d	177	static void clear_fifo(void)
189db3d4	178	{
cc789c14 UH	179	GPIFABORT = 0xff;
	180	SYNCDELAY3;
	181	FIFORESET = 0x80;
	182	SYNCDELAY3;
	183	FIFORESET = 0x82;
	184	SYNCDELAY3;
	185	FIFORESET = 0x86;
	186	SYNCDELAY3;
	187	FIFORESET = 0;
189db3d4 UH	188	}
189db3d4 UH	189
0ab4ea5d	190	static void stop_sampling(void)
189db3d4	191	{
cc789c14 UH	192	GPIFABORT = 0xff;
	193	SYNCDELAY3;
	194	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	195	}
189db3d4 UH	196
0ab4ea5d	197	static void start_sampling(void)
189db3d4	198	{
cc789c14 UH	199	int i;
cc789c14 UH	200
be6d306d UH	201	SET_ANALOG_MODE();
be6d306d UH	202
cc789c14 UH	203	clear_fifo();
	204
	205	for (i = 0; i < 1000; i++);
	206
	207	while (!(GPIFTRIG & 0x80))
	208	;
	209
	210	SYNCDELAY3;
	211	GPIFTCB1 = 0x28;
	212	SYNCDELAY3;
	213	GPIFTCB0 = 0;
	214	GPIFTRIG = (altiface == 0) ? 6 : 4;
	215
65b34f7e UH	216	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	217	LED_GREEN();
cc789c14	218	ledcounter = 0;
189db3d4 UH	219	}
189db3d4 UH	220
0ab4ea5d	221	static void select_interface(BYTE alt)
189db3d4	222	{
cc789c14	223	const BYTE *pPacketSize = \
374453b9	224	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	225	+ (9 + (16 * alt) + 9 + 4);
	226
	227	altiface = alt;
	228
	229	if (alt == 0) {
	230	/* Bulk on EP6. */
	231	EP2CFG = 0x00;
	232	EP6CFG = 0xe0;
	233	EP6GPIFFLGSEL = 1;
	234	EP6AUTOINLENL = pPacketSize[0];
	235	EP6AUTOINLENH = pPacketSize[1];
	236	} else {
	237	/* Iso on EP2. */
	238	EP2CFG = 0xd8;
	239	EP6CFG = 0x00;
	240	EP2GPIFFLGSEL = 1;
	241	EP2AUTOINLENL = pPacketSize[0];
	242	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	243	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	244	}
189db3d4 UH	245	}
189db3d4 UH	246
0ab4ea5d	247	static const struct samplerate_info {
cc789c14 UH	248	BYTE rate;
	249	BYTE wait0;
	250	BYTE wait1;
	251	BYTE opc0;
	252	BYTE opc1;
	253	BYTE out0;
	254	BYTE ifcfg;
189db3d4	255	} samplerates[] = {
374453b9 UH	256	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
374453b9 UH	257	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	258	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	259	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	260	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	261	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	262	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	263	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	264	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	265	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	266	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	267	{ 10, 240, 239, 2, 0, OUT0, 0xca },
189db3d4 UH	268	};
189db3d4 UH	269
0ab4ea5d	270	static BOOL set_samplerate(BYTE rate)
189db3d4	271	{
cc789c14 UH	272	BYTE i = 0;
	273
	274	while (samplerates[i].rate != rate) {
	275	i++;
	276	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	277	return FALSE;
	278	}
	279
	280	IFCONFIG = samplerates[i].ifcfg;
	281
	282	AUTOPTRSETUP = 7;
24373950	283	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	284	AUTOPTRL2 = 0x00;
	285
	286	/*
	287	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	288	* wait 24, CTLx=0, FIFO
	289	* wait 23, CTLx=1
	290	* jump 0, CTLx=1
cc789c14 UH	291	*
cc789c14 UH	292	* The program for 24 MHz is:
3968bbfb UH	293	* wait 1, CTLx=0, FIFO
3968bbfb UH	294	* jump 0, CTLx=1
cc789c14 UH	295	*
cc789c14 UH	296	* The program for 30/48 MHz is:
3968bbfb UH	297	* jump 0, CTLx=Z, FIFO, LOOP
	298	*
	299	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	300	*/
cc789c14 UH	301
24373950	302	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	303	EXTAUTODAT2 = samplerates[i].wait0;
	304	EXTAUTODAT2 = samplerates[i].wait1;
	305	EXTAUTODAT2 = 1;
	306	EXTAUTODAT2 = 0;
	307	EXTAUTODAT2 = 0;
	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
189db3d4	310	EXTAUTODAT2 = 0;
189db3d4	311
24373950	312	/* OPCODE 0-7 */
cc789c14 UH	313	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	314	EXTAUTODAT2 = samplerates[i].opc1;
24373950	315	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	316	EXTAUTODAT2 = 0;
	317	EXTAUTODAT2 = 0;
	318	EXTAUTODAT2 = 0;
	319	EXTAUTODAT2 = 0;
	320	EXTAUTODAT2 = 0;
	321
24373950	322	/* OUTPUT 0-7 */
cc789c14	323	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	324	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	325	EXTAUTODAT2 = OE_CTL;
24373950 UH	326	EXTAUTODAT2 = 0;
	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
	329	EXTAUTODAT2 = 0;
	330	EXTAUTODAT2 = 0;
cc789c14	331
24373950	332	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	333	EXTAUTODAT2 = 0;
	334	EXTAUTODAT2 = 0;
	335	EXTAUTODAT2 = 0;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339	EXTAUTODAT2 = 0;
	340	EXTAUTODAT2 = 0;
	341
	342	for (i = 0; i < 96; i++)
	343	EXTAUTODAT2 = 0;
	344
	345	return TRUE;
189db3d4	346	}
cc789c14	347
297fb13a UH	348	static BOOL set_calibration_pulse(BYTE fs)
	349	{
	350	switch (fs) {
	351	case 0: // 100Hz
	352	RCAP2L = -10000 & 0xff;
	353	RCAP2H = (-10000 & 0xff00) >> 8;
	354	return TRUE;
	355	case 1: // 1kHz
	356	RCAP2L = -1000 & 0xff;
	357	RCAP2H = (-1000 & 0xff00) >> 8;
	358	return TRUE;
	359	case 10: // 1kHz
	360	RCAP2L = (BYTE)(-100 & 0xff);
	361	RCAP2H = 0xff;
	362	return TRUE;
	363	case 50: // 50kHz
	364	RCAP2L = (BYTE)(-20 & 0xff);
	365	RCAP2H = 0xff;
	366	return TRUE;
	367	default:
	368	return FALSE;
	369	}
	370	}
	371
cc789c14 UH	372	/* Set alt_ifc to the current alt interface for ifc. /
	373	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	374	{
	375	(void)ifc;
	376
	377	*alt_ifc = altiface;
	378
	379	return TRUE;
189db3d4 UH	380	}
189db3d4 UH	381
cc789c14 UH	382	/*
	383	* Return TRUE if you set the interface requested.
	384	*
	385	* Note: This function should reconfigure and reset the endpoints
	386	* according to the interface descriptors you provided.
	387	*/
	388	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	389	{
	390	if (ifc == 0)
	391	select_interface(alt_ifc);
	392
	393	return TRUE;
189db3d4 UH	394	}
189db3d4 UH	395
cc789c14 UH	396	BYTE handle_get_configuration(void)
	397	{
	398	/* We only support configuration 0. */
	399	return 0;
189db3d4 UH	400	}
189db3d4 UH	401
cc789c14 UH	402	BOOL handle_set_configuration(BYTE cfg)
	403	{
	404	/* We only support configuration 0. */
	405	(void)cfg;
	406
189db3d4	407	return TRUE;
189db3d4 UH	408	}
189db3d4 UH	409
cc789c14 UH	410	BOOL handle_vendorcommand(BYTE cmd)
	411	{
	412	stop_sampling();
	413
65b34f7e UH	414	/* Set red LED, clear after timeout. */
65b34f7e UH	415	LED_RED();
cc789c14 UH	416	ledcounter = 1000;
cc789c14 UH	417
38e32023	418	/* Clear EP0BCH/L for each valid command. */
297fb13a	419	if (cmd >= 0xe0 && cmd <= 0xe6) {
cc789c14 UH	420	EP0BCH = 0;
	421	EP0BCL = 0;
	422	while (EP0CS & bmEPBUSY);
38e32023 UH	423	}
	424
	425	switch (cmd) {
	426	case 0xe0:
	427	case 0xe1:
cc789c14 UH	428	set_voltage(cmd - 0xe0, EP0BUF[0]);
	429	return TRUE;
	430	case 0xe2:
cc789c14 UH	431	set_samplerate(EP0BUF[0]);
	432	return TRUE;
	433	case 0xe3:
cc789c14 UH	434	if (EP0BUF[0] == 1)
	435	start_sampling();
	436	return TRUE;
	437	case 0xe4:
cc789c14 UH	438	set_numchannels(EP0BUF[0]);
cc789c14 UH	439	return TRUE;
297fb13a UH	440	case 0xe5:
	441	SET_COUPLING(EP0BUF[0]);
	442	return TRUE;
	443	case 0xe6:
	444	SET_CALIBRATION_PULSE(EP0BUF[0]);
	445	return TRUE;
cc789c14 UH	446	}
	447
	448	return FALSE; /* Not handled by handlers. */
	449	}
	450
0ab4ea5d	451	static void init(void)
cc789c14 UH	452	{
	453	EP4CFG = 0;
	454	EP8CFG = 0;
	455
be6d306d UH	456	SET_ANALOG_MODE();
be6d306d UH	457
cc789c14	458	/* In idle mode tristate all outputs. */
24373950 UH	459	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	460	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	461	GPIFWFSELECT = 0x00;
	462	GPIFREADYSTAT = 0x00;
	463
	464	stop_sampling();
	465
	466	set_voltage(0, 1);
	467	set_voltage(1, 1);
	468	set_samplerate(1);
	469	set_numchannels(2);
	470	select_interface(0);
189db3d4	471	}
fb4075d5	472
0ab4ea5d	473	static void main(void)
fb4075d5 UH	474	{
	475	/* Save energy. */
	476	SETCPUFREQ(CLK_12M);
	477
	478	init();
	479
	480	/* Set up interrupts. */
	481	USE_USB_INTS();
	482
	483	ENABLE_SUDAV();
	484	ENABLE_USBRESET();
	485	ENABLE_HISPEED();
	486	ENABLE_SUSPEND();
	487	ENABLE_RESUME();
	488
	489	/* Global (8051) interrupt enable. */
	490	EA = 1;
	491
	492	/* Init timer2. */
2c57c00b UH	493	RCAP2L = -TIMER2_VAL & 0xff;
2c57c00b UH	494	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
fb4075d5 UH	495	T2CON = 0;
	496	ET2 = 1;
	497	TR2 = 1;
	498
beaa03fc	499	RENUMERATE_UNCOND();
fb4075d5	500
4d971e01	501	PORTECFG = 0;
fb4075d5 UH	502	PORTCCFG = 0;
fb4075d5 UH	503	PORTACFG = 0;
4d971e01	504	OEE = 0xff;
fb4075d5	505	OEC = 0xff;
4d971e01	506	OEA = 0xff;
fb4075d5 UH	507
	508	while (TRUE) {
	509	if (dosud) {
	510	dosud = FALSE;
	511	handle_setupdata();
	512	}
	513
	514	if (dosuspend) {
	515	dosuspend = FALSE;
	516	do {
	517	/* Make sure ext wakeups are cleared. */
3968bbfb	518	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	519	SUSPEND = 1;
	520	PCON \|= 1;
	521	__asm
	522	nop
	523	nop
	524	nop
	525	nop
	526	nop
	527	nop
	528	nop
	529	__endasm;
	530	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	531
	532	/* Resume (TRM 6.4). */
	533	if (REMOTE_WAKEUP()) {
	534	delay(5);
	535	USBCS \|= bmSIGRESUME;
	536	delay(15);
	537	USBCS &= ~bmSIGRESUME;
	538	}
	539	}
	540	}
	541	}