[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE()

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE()
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7
	31
65b34f7e UH	32	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	33	#define LED_GREEN() PC0 = 1; PC1 = 0;
	34	#define LED_RED() PC0 = 0; PC1 = 1;
	35
e1c5ba21 UH	36	/* CTLx pin index (IFCLK, ADC clock input). */
	37	#define CTL_BIT 2
	38
	39	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	40	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	41
cc789c14	42	/* Change to support as many interfaces as you need. */
0ab4ea5d	43	static BYTE altiface = 0;
189db3d4	44
0ab4ea5d	45	static volatile WORD ledcounter = 0;
189db3d4	46
0ab4ea5d UH	47	static volatile __bit dosud = FALSE;
0ab4ea5d UH	48	static volatile __bit dosuspend = FALSE;
cc789c14 UH	49
	50	extern __code BYTE highspd_dscr;
	51	extern __code BYTE fullspd_dscr;
189db3d4	52
cc789c14 UH	53	void resume_isr(void) __interrupt RESUME_ISR
	54	{
	55	CLEAR_RESUME();
189db3d4	56	}
cc789c14 UH	57
	58	void sudav_isr(void) __interrupt SUDAV_ISR
	59	{
	60	dosud = TRUE;
	61	CLEAR_SUDAV();
189db3d4	62	}
cc789c14 UH	63
	64	void usbreset_isr(void) __interrupt USBRESET_ISR
	65	{
	66	handle_hispeed(FALSE);
	67	CLEAR_USBRESET();
189db3d4	68	}
cc789c14 UH	69
	70	void hispeed_isr(void) __interrupt HISPEED_ISR
	71	{
	72	handle_hispeed(TRUE);
	73	CLEAR_HISPEED();
189db3d4 UH	74	}
189db3d4 UH	75
cc789c14 UH	76	void suspend_isr(void) __interrupt SUSPEND_ISR
	77	{
	78	dosuspend = TRUE;
	79	CLEAR_SUSPEND();
189db3d4 UH	80	}
189db3d4 UH	81
cc789c14 UH	82	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	83	{
e583c3fc	84	TOGGLE_CALIBRATION_PIN();
3968bbfb	85
65b34f7e UH	86	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	87	LED_CLEAR();
3968bbfb	88
cc789c14	89	TF2 = 0;
189db3d4	90	}
189db3d4	91
cc789c14 UH	92	/*
cc789c14 UH	93	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	94	* For channel 0 we want to set bits 5, 6 & 7
	95	* For channel 1 we want to set bits 2, 3 & 4
	96	*
cc789c14 UH	97	* We convert the input values that are strange due to original
	98	* firmware code into the value of the three bits as follows:
	99	*
189db3d4 UH	100	* val -> bits
	101	* 1 -> 010b
	102	* 2 -> 001b
	103	* 5 -> 000b
	104	* 10 -> 011b
	105	*
cc789c14 UH	106	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	107	* in the serial selector chip.
189db3d4 UH	108	*
	109	* The multiplication of the converted value by 0x24 sets the relevant bits in
	110	* both channels and then we mask it out to only affect the channel currently
	111	* requested.
	112	*/
0ab4ea5d	113	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	114	{
cc789c14 UH	115	BYTE bits, mask;
	116
	117	switch (val) {
	118	case 1:
	119	bits = 0x24 * 2;
	120	break;
	121	case 2:
	122	bits = 0x24 * 1;
	123	break;
	124	case 5:
	125	bits = 0x24 * 0;
	126	break;
	127	case 10:
	128	bits = 0x24 * 3;
	129	break;
	130	default:
	131	return FALSE;
	132	}
	133
	134	mask = (channel) ? 0xe0 : 0x1c;
	135	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	136
cc789c14	137	return TRUE;
189db3d4 UH	138	}
189db3d4 UH	139
0ab4ea5d	140	static BOOL set_numchannels(BYTE numchannels)
189db3d4	141	{
cc789c14 UH	142	if (numchannels == 1 \|\| numchannels == 2) {
	143	BYTE fifocfg = 7 + numchannels;
	144	EP2FIFOCFG = fifocfg;
	145	EP6FIFOCFG = fifocfg;
	146	return TRUE;
	147	}
	148
	149	return FALSE;
189db3d4 UH	150	}
189db3d4 UH	151
0ab4ea5d	152	static void clear_fifo(void)
189db3d4	153	{
cc789c14 UH	154	GPIFABORT = 0xff;
	155	SYNCDELAY3;
	156	FIFORESET = 0x80;
	157	SYNCDELAY3;
	158	FIFORESET = 0x82;
	159	SYNCDELAY3;
	160	FIFORESET = 0x86;
	161	SYNCDELAY3;
	162	FIFORESET = 0;
189db3d4 UH	163	}
189db3d4 UH	164
0ab4ea5d	165	static void stop_sampling(void)
189db3d4	166	{
cc789c14 UH	167	GPIFABORT = 0xff;
	168	SYNCDELAY3;
	169	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	170	}
189db3d4 UH	171
0ab4ea5d	172	static void start_sampling(void)
189db3d4	173	{
cc789c14 UH	174	int i;
cc789c14 UH	175
be6d306d UH	176	SET_ANALOG_MODE();
be6d306d UH	177
cc789c14 UH	178	clear_fifo();
	179
	180	for (i = 0; i < 1000; i++);
	181
	182	while (!(GPIFTRIG & 0x80))
	183	;
	184
	185	SYNCDELAY3;
	186	GPIFTCB1 = 0x28;
	187	SYNCDELAY3;
	188	GPIFTCB0 = 0;
	189	GPIFTRIG = (altiface == 0) ? 6 : 4;
	190
65b34f7e UH	191	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	192	LED_GREEN();
cc789c14	193	ledcounter = 0;
189db3d4 UH	194	}
189db3d4 UH	195
0ab4ea5d	196	static void select_interface(BYTE alt)
189db3d4	197	{
cc789c14	198	const BYTE *pPacketSize = \
374453b9	199	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	200	+ (9 + (16 * alt) + 9 + 4);
	201
	202	altiface = alt;
	203
	204	if (alt == 0) {
	205	/* Bulk on EP6. */
	206	EP2CFG = 0x00;
	207	EP6CFG = 0xe0;
	208	EP6GPIFFLGSEL = 1;
	209	EP6AUTOINLENL = pPacketSize[0];
	210	EP6AUTOINLENH = pPacketSize[1];
	211	} else {
	212	/* Iso on EP2. */
	213	EP2CFG = 0xd8;
	214	EP6CFG = 0x00;
	215	EP2GPIFFLGSEL = 1;
	216	EP2AUTOINLENL = pPacketSize[0];
	217	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	218	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	219	}
189db3d4 UH	220	}
189db3d4 UH	221
0ab4ea5d	222	static const struct samplerate_info {
cc789c14 UH	223	BYTE rate;
	224	BYTE wait0;
	225	BYTE wait1;
	226	BYTE opc0;
	227	BYTE opc1;
	228	BYTE out0;
	229	BYTE ifcfg;
189db3d4	230	} samplerates[] = {
374453b9 UH	231	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
374453b9 UH	232	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	233	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	234	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	235	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	236	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	237	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	238	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	239	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	240	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	241	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	242	{ 10, 240, 239, 2, 0, OUT0, 0xca },
189db3d4 UH	243	};
189db3d4 UH	244
0ab4ea5d	245	static BOOL set_samplerate(BYTE rate)
189db3d4	246	{
cc789c14 UH	247	BYTE i = 0;
	248
	249	while (samplerates[i].rate != rate) {
	250	i++;
	251	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	252	return FALSE;
	253	}
	254
	255	IFCONFIG = samplerates[i].ifcfg;
	256
	257	AUTOPTRSETUP = 7;
24373950	258	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	259	AUTOPTRL2 = 0x00;
	260
	261	/*
	262	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	263	* wait 24, CTLx=0, FIFO
	264	* wait 23, CTLx=1
	265	* jump 0, CTLx=1
cc789c14 UH	266	*
cc789c14 UH	267	* The program for 24 MHz is:
3968bbfb UH	268	* wait 1, CTLx=0, FIFO
3968bbfb UH	269	* jump 0, CTLx=1
cc789c14 UH	270	*
cc789c14 UH	271	* The program for 30/48 MHz is:
3968bbfb UH	272	* jump 0, CTLx=Z, FIFO, LOOP
	273	*
	274	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	275	*/
cc789c14 UH	276
24373950	277	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	278	EXTAUTODAT2 = samplerates[i].wait0;
	279	EXTAUTODAT2 = samplerates[i].wait1;
	280	EXTAUTODAT2 = 1;
	281	EXTAUTODAT2 = 0;
	282	EXTAUTODAT2 = 0;
	283	EXTAUTODAT2 = 0;
	284	EXTAUTODAT2 = 0;
189db3d4	285	EXTAUTODAT2 = 0;
189db3d4	286
24373950	287	/* OPCODE 0-7 */
cc789c14 UH	288	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	289	EXTAUTODAT2 = samplerates[i].opc1;
24373950	290	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	291	EXTAUTODAT2 = 0;
	292	EXTAUTODAT2 = 0;
	293	EXTAUTODAT2 = 0;
	294	EXTAUTODAT2 = 0;
	295	EXTAUTODAT2 = 0;
	296
24373950	297	/* OUTPUT 0-7 */
cc789c14	298	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	299	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	300	EXTAUTODAT2 = OE_CTL;
24373950 UH	301	EXTAUTODAT2 = 0;
	302	EXTAUTODAT2 = 0;
	303	EXTAUTODAT2 = 0;
	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
cc789c14	306
24373950	307	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
	310	EXTAUTODAT2 = 0;
	311	EXTAUTODAT2 = 0;
	312	EXTAUTODAT2 = 0;
	313	EXTAUTODAT2 = 0;
	314	EXTAUTODAT2 = 0;
	315	EXTAUTODAT2 = 0;
	316
	317	for (i = 0; i < 96; i++)
	318	EXTAUTODAT2 = 0;
	319
	320	return TRUE;
189db3d4	321	}
cc789c14 UH	322
	323	/* Set alt_ifc to the current alt interface for ifc. /
	324	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	325	{
	326	(void)ifc;
	327
	328	*alt_ifc = altiface;
	329
	330	return TRUE;
189db3d4 UH	331	}
189db3d4 UH	332
cc789c14 UH	333	/*
	334	* Return TRUE if you set the interface requested.
	335	*
	336	* Note: This function should reconfigure and reset the endpoints
	337	* according to the interface descriptors you provided.
	338	*/
	339	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	340	{
	341	if (ifc == 0)
	342	select_interface(alt_ifc);
	343
	344	return TRUE;
189db3d4 UH	345	}
189db3d4 UH	346
cc789c14 UH	347	BYTE handle_get_configuration(void)
	348	{
	349	/* We only support configuration 0. */
	350	return 0;
189db3d4 UH	351	}
189db3d4 UH	352
cc789c14 UH	353	BOOL handle_set_configuration(BYTE cfg)
	354	{
	355	/* We only support configuration 0. */
	356	(void)cfg;
	357
189db3d4	358	return TRUE;
189db3d4 UH	359	}
189db3d4 UH	360
cc789c14 UH	361	BOOL handle_vendorcommand(BYTE cmd)
	362	{
	363	stop_sampling();
	364
65b34f7e UH	365	/* Set red LED, clear after timeout. */
65b34f7e UH	366	LED_RED();
cc789c14 UH	367	ledcounter = 1000;
cc789c14 UH	368
38e32023 UH	369	/* Clear EP0BCH/L for each valid command. */
38e32023 UH	370	if (cmd >= 0xe0 && cmd <= 0xe4) {
cc789c14 UH	371	EP0BCH = 0;
	372	EP0BCL = 0;
	373	while (EP0CS & bmEPBUSY);
38e32023 UH	374	}
	375
	376	switch (cmd) {
	377	case 0xe0:
	378	case 0xe1:
cc789c14 UH	379	set_voltage(cmd - 0xe0, EP0BUF[0]);
	380	return TRUE;
	381	case 0xe2:
cc789c14 UH	382	set_samplerate(EP0BUF[0]);
	383	return TRUE;
	384	case 0xe3:
cc789c14 UH	385	if (EP0BUF[0] == 1)
	386	start_sampling();
	387	return TRUE;
	388	case 0xe4:
cc789c14 UH	389	set_numchannels(EP0BUF[0]);
	390	return TRUE;
	391	}
	392
	393	return FALSE; /* Not handled by handlers. */
	394	}
	395
0ab4ea5d	396	static void init(void)
cc789c14 UH	397	{
	398	EP4CFG = 0;
	399	EP8CFG = 0;
	400
be6d306d UH	401	SET_ANALOG_MODE();
be6d306d UH	402
cc789c14	403	/* In idle mode tristate all outputs. */
24373950 UH	404	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	405	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	406	GPIFWFSELECT = 0x00;
	407	GPIFREADYSTAT = 0x00;
	408
	409	stop_sampling();
	410
	411	set_voltage(0, 1);
	412	set_voltage(1, 1);
	413	set_samplerate(1);
	414	set_numchannels(2);
	415	select_interface(0);
189db3d4	416	}
fb4075d5	417
0ab4ea5d	418	static void main(void)
fb4075d5 UH	419	{
	420	/* Save energy. */
	421	SETCPUFREQ(CLK_12M);
	422
	423	init();
	424
	425	/* Set up interrupts. */
	426	USE_USB_INTS();
	427
	428	ENABLE_SUDAV();
	429	ENABLE_USBRESET();
	430	ENABLE_HISPEED();
	431	ENABLE_SUSPEND();
	432	ENABLE_RESUME();
	433
	434	/* Global (8051) interrupt enable. */
	435	EA = 1;
	436
	437	/* Init timer2. */
	438	RCAP2L = -500 & 0xff;
386296a7	439	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	440	T2CON = 0;
	441	ET2 = 1;
	442	TR2 = 1;
	443
beaa03fc	444	RENUMERATE_UNCOND();
fb4075d5	445
4d971e01	446	PORTECFG = 0;
fb4075d5 UH	447	PORTCCFG = 0;
fb4075d5 UH	448	PORTACFG = 0;
4d971e01	449	OEE = 0xff;
fb4075d5	450	OEC = 0xff;
4d971e01	451	OEA = 0xff;
fb4075d5 UH	452
	453	while (TRUE) {
	454	if (dosud) {
	455	dosud = FALSE;
	456	handle_setupdata();
	457	}
	458
	459	if (dosuspend) {
	460	dosuspend = FALSE;
	461	do {
	462	/* Make sure ext wakeups are cleared. */
3968bbfb	463	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	464	SUSPEND = 1;
	465	PCON \|= 1;
	466	__asm
	467	nop
	468	nop
	469	nop
	470	nop
	471	nop
	472	nop
	473	nop
	474	__endasm;
	475	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	476
	477	/* Resume (TRM 6.4). */
	478	if (REMOTE_WAKEUP()) {
	479	delay(5);
	480	USBCS \|= bmSIGRESUME;
	481	delay(15);
	482	USBCS &= ~bmSIGRESUME;
	483	}
	484	}
	485	}
	486	}