[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE()

#define SET_COUPLING(x)

#define SET_CALIBRATION_PULSE(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE()
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x)
	30
	31	#define SET_CALIBRATION_PULSE(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7
	35
65b34f7e UH	36	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	37	#define LED_GREEN() PC0 = 1; PC1 = 0;
	38	#define LED_RED() PC0 = 0; PC1 = 1;
	39
e1c5ba21 UH	40	/* CTLx pin index (IFCLK, ADC clock input). */
	41	#define CTL_BIT 2
	42
	43	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	44	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	45
cc789c14	46	/* Change to support as many interfaces as you need. */
0ab4ea5d	47	static BYTE altiface = 0;
189db3d4	48
0ab4ea5d	49	static volatile WORD ledcounter = 0;
189db3d4	50
0ab4ea5d UH	51	static volatile __bit dosud = FALSE;
0ab4ea5d UH	52	static volatile __bit dosuspend = FALSE;
cc789c14 UH	53
	54	extern __code BYTE highspd_dscr;
	55	extern __code BYTE fullspd_dscr;
189db3d4	56
cc789c14 UH	57	void resume_isr(void) __interrupt RESUME_ISR
	58	{
	59	CLEAR_RESUME();
189db3d4	60	}
cc789c14 UH	61
	62	void sudav_isr(void) __interrupt SUDAV_ISR
	63	{
	64	dosud = TRUE;
	65	CLEAR_SUDAV();
189db3d4	66	}
cc789c14 UH	67
	68	void usbreset_isr(void) __interrupt USBRESET_ISR
	69	{
	70	handle_hispeed(FALSE);
	71	CLEAR_USBRESET();
189db3d4	72	}
cc789c14 UH	73
	74	void hispeed_isr(void) __interrupt HISPEED_ISR
	75	{
	76	handle_hispeed(TRUE);
	77	CLEAR_HISPEED();
189db3d4 UH	78	}
189db3d4 UH	79
cc789c14 UH	80	void suspend_isr(void) __interrupt SUSPEND_ISR
	81	{
	82	dosuspend = TRUE;
	83	CLEAR_SUSPEND();
189db3d4 UH	84	}
189db3d4 UH	85
cc789c14 UH	86	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	87	{
e583c3fc	88	TOGGLE_CALIBRATION_PIN();
3968bbfb	89
65b34f7e UH	90	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	91	LED_CLEAR();
3968bbfb	92
cc789c14	93	TF2 = 0;
189db3d4	94	}
189db3d4	95
cc789c14 UH	96	/*
cc789c14 UH	97	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	98	* For channel 0 we want to set bits 5, 6 & 7
	99	* For channel 1 we want to set bits 2, 3 & 4
	100	*
cc789c14 UH	101	* We convert the input values that are strange due to original
	102	* firmware code into the value of the three bits as follows:
	103	*
189db3d4 UH	104	* val -> bits
	105	* 1 -> 010b
	106	* 2 -> 001b
	107	* 5 -> 000b
	108	* 10 -> 011b
	109	*
cc789c14 UH	110	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	111	* in the serial selector chip.
189db3d4 UH	112	*
	113	* The multiplication of the converted value by 0x24 sets the relevant bits in
	114	* both channels and then we mask it out to only affect the channel currently
	115	* requested.
	116	*/
0ab4ea5d	117	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	118	{
cc789c14 UH	119	BYTE bits, mask;
	120
	121	switch (val) {
	122	case 1:
	123	bits = 0x24 * 2;
	124	break;
	125	case 2:
	126	bits = 0x24 * 1;
	127	break;
	128	case 5:
	129	bits = 0x24 * 0;
	130	break;
	131	case 10:
	132	bits = 0x24 * 3;
	133	break;
	134	default:
	135	return FALSE;
	136	}
	137
	138	mask = (channel) ? 0xe0 : 0x1c;
	139	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	140
cc789c14	141	return TRUE;
189db3d4 UH	142	}
189db3d4 UH	143
297fb13a UH	144	/**
	145	* Each LSB in the nibble of the byte controls the coupling per channel.
	146	*
	147	* Setting PE3 disables AC coupling capacitor on CH0.
	148	* Setting PE0 disables AC coupling capacitor on CH1.
	149	*/
	150	static void set_coupling(BYTE coupling_cfg)
	151	{
	152	if (coupling_cfg & 0x01)
	153	IOE \|= 0x08;
	154	else
	155	IOE &= ~0x08;
	156
	157	if (coupling_cfg & 0x10)
	158	IOE \|= 0x01;
	159	else
	160	IOE &= ~0x01;
	161	}
	162
0ab4ea5d	163	static BOOL set_numchannels(BYTE numchannels)
189db3d4	164	{
cc789c14 UH	165	if (numchannels == 1 \|\| numchannels == 2) {
	166	BYTE fifocfg = 7 + numchannels;
	167	EP2FIFOCFG = fifocfg;
	168	EP6FIFOCFG = fifocfg;
	169	return TRUE;
	170	}
	171
	172	return FALSE;
189db3d4 UH	173	}
189db3d4 UH	174
0ab4ea5d	175	static void clear_fifo(void)
189db3d4	176	{
cc789c14 UH	177	GPIFABORT = 0xff;
	178	SYNCDELAY3;
	179	FIFORESET = 0x80;
	180	SYNCDELAY3;
	181	FIFORESET = 0x82;
	182	SYNCDELAY3;
	183	FIFORESET = 0x86;
	184	SYNCDELAY3;
	185	FIFORESET = 0;
189db3d4 UH	186	}
189db3d4 UH	187
0ab4ea5d	188	static void stop_sampling(void)
189db3d4	189	{
cc789c14 UH	190	GPIFABORT = 0xff;
	191	SYNCDELAY3;
	192	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	193	}
189db3d4 UH	194
0ab4ea5d	195	static void start_sampling(void)
189db3d4	196	{
cc789c14 UH	197	int i;
cc789c14 UH	198
be6d306d UH	199	SET_ANALOG_MODE();
be6d306d UH	200
cc789c14 UH	201	clear_fifo();
	202
	203	for (i = 0; i < 1000; i++);
	204
	205	while (!(GPIFTRIG & 0x80))
	206	;
	207
	208	SYNCDELAY3;
	209	GPIFTCB1 = 0x28;
	210	SYNCDELAY3;
	211	GPIFTCB0 = 0;
	212	GPIFTRIG = (altiface == 0) ? 6 : 4;
	213
65b34f7e UH	214	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	215	LED_GREEN();
cc789c14	216	ledcounter = 0;
189db3d4 UH	217	}
189db3d4 UH	218
0ab4ea5d	219	static void select_interface(BYTE alt)
189db3d4	220	{
cc789c14	221	const BYTE *pPacketSize = \
374453b9	222	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	223	+ (9 + (16 * alt) + 9 + 4);
	224
	225	altiface = alt;
	226
	227	if (alt == 0) {
	228	/* Bulk on EP6. */
	229	EP2CFG = 0x00;
	230	EP6CFG = 0xe0;
	231	EP6GPIFFLGSEL = 1;
	232	EP6AUTOINLENL = pPacketSize[0];
	233	EP6AUTOINLENH = pPacketSize[1];
	234	} else {
	235	/* Iso on EP2. */
	236	EP2CFG = 0xd8;
	237	EP6CFG = 0x00;
	238	EP2GPIFFLGSEL = 1;
	239	EP2AUTOINLENL = pPacketSize[0];
	240	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	241	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	242	}
189db3d4 UH	243	}
189db3d4 UH	244
0ab4ea5d	245	static const struct samplerate_info {
cc789c14 UH	246	BYTE rate;
	247	BYTE wait0;
	248	BYTE wait1;
	249	BYTE opc0;
	250	BYTE opc1;
	251	BYTE out0;
	252	BYTE ifcfg;
189db3d4	253	} samplerates[] = {
374453b9 UH	254	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
374453b9 UH	255	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	256	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	257	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	258	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	259	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	260	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	261	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	262	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	263	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	264	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	265	{ 10, 240, 239, 2, 0, OUT0, 0xca },
189db3d4 UH	266	};
189db3d4 UH	267
0ab4ea5d	268	static BOOL set_samplerate(BYTE rate)
189db3d4	269	{
cc789c14 UH	270	BYTE i = 0;
	271
	272	while (samplerates[i].rate != rate) {
	273	i++;
	274	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	275	return FALSE;
	276	}
	277
	278	IFCONFIG = samplerates[i].ifcfg;
	279
	280	AUTOPTRSETUP = 7;
24373950	281	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	282	AUTOPTRL2 = 0x00;
	283
	284	/*
	285	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	286	* wait 24, CTLx=0, FIFO
	287	* wait 23, CTLx=1
	288	* jump 0, CTLx=1
cc789c14 UH	289	*
cc789c14 UH	290	* The program for 24 MHz is:
3968bbfb UH	291	* wait 1, CTLx=0, FIFO
3968bbfb UH	292	* jump 0, CTLx=1
cc789c14 UH	293	*
cc789c14 UH	294	* The program for 30/48 MHz is:
3968bbfb UH	295	* jump 0, CTLx=Z, FIFO, LOOP
	296	*
	297	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	298	*/
cc789c14 UH	299
24373950	300	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	301	EXTAUTODAT2 = samplerates[i].wait0;
	302	EXTAUTODAT2 = samplerates[i].wait1;
	303	EXTAUTODAT2 = 1;
	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
	306	EXTAUTODAT2 = 0;
	307	EXTAUTODAT2 = 0;
189db3d4	308	EXTAUTODAT2 = 0;
189db3d4	309
24373950	310	/* OPCODE 0-7 */
cc789c14 UH	311	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	312	EXTAUTODAT2 = samplerates[i].opc1;
24373950	313	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	314	EXTAUTODAT2 = 0;
	315	EXTAUTODAT2 = 0;
	316	EXTAUTODAT2 = 0;
	317	EXTAUTODAT2 = 0;
	318	EXTAUTODAT2 = 0;
	319
24373950	320	/* OUTPUT 0-7 */
cc789c14	321	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	322	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	323	EXTAUTODAT2 = OE_CTL;
24373950 UH	324	EXTAUTODAT2 = 0;
	325	EXTAUTODAT2 = 0;
	326	EXTAUTODAT2 = 0;
	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
cc789c14	329
24373950	330	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	331	EXTAUTODAT2 = 0;
	332	EXTAUTODAT2 = 0;
	333	EXTAUTODAT2 = 0;
	334	EXTAUTODAT2 = 0;
	335	EXTAUTODAT2 = 0;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339
	340	for (i = 0; i < 96; i++)
	341	EXTAUTODAT2 = 0;
	342
	343	return TRUE;
189db3d4	344	}
cc789c14	345
297fb13a UH	346	static BOOL set_calibration_pulse(BYTE fs)
	347	{
	348	switch (fs) {
	349	case 0: // 100Hz
	350	RCAP2L = -10000 & 0xff;
	351	RCAP2H = (-10000 & 0xff00) >> 8;
	352	return TRUE;
	353	case 1: // 1kHz
	354	RCAP2L = -1000 & 0xff;
	355	RCAP2H = (-1000 & 0xff00) >> 8;
	356	return TRUE;
	357	case 10: // 1kHz
	358	RCAP2L = (BYTE)(-100 & 0xff);
	359	RCAP2H = 0xff;
	360	return TRUE;
	361	case 50: // 50kHz
	362	RCAP2L = (BYTE)(-20 & 0xff);
	363	RCAP2H = 0xff;
	364	return TRUE;
	365	default:
	366	return FALSE;
	367	}
	368	}
	369
cc789c14 UH	370	/* Set alt_ifc to the current alt interface for ifc. /
	371	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	372	{
	373	(void)ifc;
	374
	375	*alt_ifc = altiface;
	376
	377	return TRUE;
189db3d4 UH	378	}
189db3d4 UH	379
cc789c14 UH	380	/*
	381	* Return TRUE if you set the interface requested.
	382	*
	383	* Note: This function should reconfigure and reset the endpoints
	384	* according to the interface descriptors you provided.
	385	*/
	386	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	387	{
	388	if (ifc == 0)
	389	select_interface(alt_ifc);
	390
	391	return TRUE;
189db3d4 UH	392	}
189db3d4 UH	393
cc789c14 UH	394	BYTE handle_get_configuration(void)
	395	{
	396	/* We only support configuration 0. */
	397	return 0;
189db3d4 UH	398	}
189db3d4 UH	399
cc789c14 UH	400	BOOL handle_set_configuration(BYTE cfg)
	401	{
	402	/* We only support configuration 0. */
	403	(void)cfg;
	404
189db3d4	405	return TRUE;
189db3d4 UH	406	}
189db3d4 UH	407
cc789c14 UH	408	BOOL handle_vendorcommand(BYTE cmd)
	409	{
	410	stop_sampling();
	411
65b34f7e UH	412	/* Set red LED, clear after timeout. */
65b34f7e UH	413	LED_RED();
cc789c14 UH	414	ledcounter = 1000;
cc789c14 UH	415
38e32023	416	/* Clear EP0BCH/L for each valid command. */
297fb13a	417	if (cmd >= 0xe0 && cmd <= 0xe6) {
cc789c14 UH	418	EP0BCH = 0;
	419	EP0BCL = 0;
	420	while (EP0CS & bmEPBUSY);
38e32023 UH	421	}
	422
	423	switch (cmd) {
	424	case 0xe0:
	425	case 0xe1:
cc789c14 UH	426	set_voltage(cmd - 0xe0, EP0BUF[0]);
	427	return TRUE;
	428	case 0xe2:
cc789c14 UH	429	set_samplerate(EP0BUF[0]);
	430	return TRUE;
	431	case 0xe3:
cc789c14 UH	432	if (EP0BUF[0] == 1)
	433	start_sampling();
	434	return TRUE;
	435	case 0xe4:
cc789c14 UH	436	set_numchannels(EP0BUF[0]);
cc789c14 UH	437	return TRUE;
297fb13a UH	438	case 0xe5:
	439	SET_COUPLING(EP0BUF[0]);
	440	return TRUE;
	441	case 0xe6:
	442	SET_CALIBRATION_PULSE(EP0BUF[0]);
	443	return TRUE;
cc789c14 UH	444	}
	445
	446	return FALSE; /* Not handled by handlers. */
	447	}
	448
0ab4ea5d	449	static void init(void)
cc789c14 UH	450	{
	451	EP4CFG = 0;
	452	EP8CFG = 0;
	453
be6d306d UH	454	SET_ANALOG_MODE();
be6d306d UH	455
cc789c14	456	/* In idle mode tristate all outputs. */
24373950 UH	457	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	458	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	459	GPIFWFSELECT = 0x00;
	460	GPIFREADYSTAT = 0x00;
	461
	462	stop_sampling();
	463
	464	set_voltage(0, 1);
	465	set_voltage(1, 1);
	466	set_samplerate(1);
	467	set_numchannels(2);
	468	select_interface(0);
189db3d4	469	}
fb4075d5	470
0ab4ea5d	471	static void main(void)
fb4075d5 UH	472	{
	473	/* Save energy. */
	474	SETCPUFREQ(CLK_12M);
	475
	476	init();
	477
	478	/* Set up interrupts. */
	479	USE_USB_INTS();
	480
	481	ENABLE_SUDAV();
	482	ENABLE_USBRESET();
	483	ENABLE_HISPEED();
	484	ENABLE_SUSPEND();
	485	ENABLE_RESUME();
	486
	487	/* Global (8051) interrupt enable. */
	488	EA = 1;
	489
	490	/* Init timer2. */
	491	RCAP2L = -500 & 0xff;
386296a7	492	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	493	T2CON = 0;
	494	ET2 = 1;
	495	TR2 = 1;
	496
beaa03fc	497	RENUMERATE_UNCOND();
fb4075d5	498
4d971e01	499	PORTECFG = 0;
fb4075d5 UH	500	PORTCCFG = 0;
fb4075d5 UH	501	PORTACFG = 0;
4d971e01	502	OEE = 0xff;
fb4075d5	503	OEC = 0xff;
4d971e01	504	OEA = 0xff;
fb4075d5 UH	505
	506	while (TRUE) {
	507	if (dosud) {
	508	dosud = FALSE;
	509	handle_setupdata();
	510	}
	511
	512	if (dosuspend) {
	513	dosuspend = FALSE;
	514	do {
	515	/* Make sure ext wakeups are cleared. */
3968bbfb	516	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	517	SUSPEND = 1;
	518	PCON \|= 1;
	519	__asm
	520	nop
	521	nop
	522	nop
	523	nop
	524	nop
	525	nop
	526	nop
	527	__endasm;
	528	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	529
	530	/* Resume (TRM 6.4). */
	531	if (REMOTE_WAKEUP()) {
	532	delay(5);
	533	USBCS \|= bmSIGRESUME;
	534	delay(15);
	535	USBCS &= ~bmSIGRESUME;
	536	}
	537	}
	538	}
	539	}