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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
28a35d8a HE |
8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
911f1834 | 23 | /* |
6352d030 | 24 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
25 | */ |
26 | ||
6ec6c43b | 27 | #include <config.h> |
3ba56876 | 28 | #include "protocol.h" |
28a35d8a | 29 | |
b1648dea | 30 | /* |
b65649f6 GS |
31 | * The ASIX SIGMA hardware supports fixed 200MHz and 100MHz sample rates |
32 | * (by means of separate firmware images). As well as 50MHz divided by | |
33 | * an integer divider in the 1..256 range (by the "typical" firmware). | |
34 | * Which translates to a strict lower boundary of around 195kHz. | |
35 | * | |
36 | * This driver "suggests" a subset of the available rates by listing a | |
37 | * few discrete values, while setter routines accept any user specified | |
38 | * rate that is supported by the hardware. | |
b1648dea | 39 | */ |
abcd4771 | 40 | static const uint64_t samplerates[] = { |
b65649f6 GS |
41 | /* 50MHz and integer divider. 1/2/5 steps (where possible). */ |
42 | SR_KHZ(200), SR_KHZ(500), | |
43 | SR_MHZ(1), SR_MHZ(2), SR_MHZ(5), | |
44 | SR_MHZ(10), SR_MHZ(25), SR_MHZ(50), | |
45 | /* 100MHz/200MHz, fixed rates in special firmware. */ | |
46 | SR_MHZ(100), SR_MHZ(200), | |
28a35d8a HE |
47 | }; |
48 | ||
abcd4771 GS |
49 | SR_PRIV GVariant *sigma_get_samplerates_list(void) |
50 | { | |
51 | return std_gvar_samplerates(samplerates, ARRAY_SIZE(samplerates)); | |
52 | } | |
39c64c6a | 53 | |
742368a2 | 54 | static const char *firmware_files[] = { |
80e717b3 GS |
55 | [SIGMA_FW_50MHZ] = "asix-sigma-50.fw", /* 50MHz, 8bit divider. */ |
56 | [SIGMA_FW_100MHZ] = "asix-sigma-100.fw", /* 100MHz, fixed. */ | |
57 | [SIGMA_FW_200MHZ] = "asix-sigma-200.fw", /* 200MHz, fixed. */ | |
58 | [SIGMA_FW_SYNC] = "asix-sigma-50sync.fw", /* Sync from external pin. */ | |
59 | [SIGMA_FW_FREQ] = "asix-sigma-phasor.fw", /* Frequency counter. */ | |
f6564c8d HE |
60 | }; |
61 | ||
742368a2 GS |
62 | #define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024) |
63 | ||
7fe1f91f GS |
64 | static int sigma_ftdi_open(const struct sr_dev_inst *sdi) |
65 | { | |
66 | struct dev_context *devc; | |
67 | int vid, pid; | |
68 | const char *serno; | |
69 | int ret; | |
70 | ||
71 | devc = sdi->priv; | |
72 | if (!devc) | |
73 | return SR_ERR_ARG; | |
74 | ||
75 | if (devc->ftdi.is_open) | |
76 | return SR_OK; | |
77 | ||
78 | vid = devc->id.vid; | |
79 | pid = devc->id.pid; | |
80 | serno = sdi->serial_num; | |
81 | if (!vid || !pid || !serno || !*serno) | |
82 | return SR_ERR_ARG; | |
83 | ||
84 | ret = ftdi_init(&devc->ftdi.ctx); | |
85 | if (ret < 0) { | |
86 | sr_err("Cannot initialize FTDI context (%d): %s.", | |
87 | ret, ftdi_get_error_string(&devc->ftdi.ctx)); | |
88 | return SR_ERR_IO; | |
89 | } | |
90 | ret = ftdi_usb_open_desc_index(&devc->ftdi.ctx, | |
91 | vid, pid, NULL, serno, 0); | |
92 | if (ret < 0) { | |
93 | sr_err("Cannot open device (%d): %s.", | |
94 | ret, ftdi_get_error_string(&devc->ftdi.ctx)); | |
95 | return SR_ERR_IO; | |
96 | } | |
97 | devc->ftdi.is_open = TRUE; | |
98 | ||
99 | return SR_OK; | |
100 | } | |
101 | ||
102 | static int sigma_ftdi_close(struct dev_context *devc) | |
103 | { | |
104 | int ret; | |
105 | ||
106 | ret = ftdi_usb_close(&devc->ftdi.ctx); | |
107 | devc->ftdi.is_open = FALSE; | |
108 | devc->ftdi.must_close = FALSE; | |
109 | ftdi_deinit(&devc->ftdi.ctx); | |
110 | ||
111 | return ret == 0 ? SR_OK : SR_ERR_IO; | |
112 | } | |
113 | ||
114 | SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi) | |
115 | { | |
116 | struct dev_context *devc; | |
117 | int ret; | |
118 | ||
119 | if (!sdi) | |
120 | return SR_ERR_ARG; | |
121 | devc = sdi->priv; | |
122 | if (!devc) | |
123 | return SR_ERR_ARG; | |
124 | ||
125 | if (devc->ftdi.is_open) | |
126 | return SR_OK; | |
127 | ||
128 | ret = sigma_ftdi_open(sdi); | |
129 | if (ret != SR_OK) | |
130 | return ret; | |
131 | devc->ftdi.must_close = TRUE; | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
136 | SR_PRIV int sigma_check_close(struct dev_context *devc) | |
137 | { | |
138 | int ret; | |
139 | ||
140 | if (!devc) | |
141 | return SR_ERR_ARG; | |
142 | ||
143 | if (devc->ftdi.must_close) { | |
144 | ret = sigma_ftdi_close(devc); | |
145 | if (ret != SR_OK) | |
146 | return ret; | |
147 | devc->ftdi.must_close = FALSE; | |
148 | } | |
149 | ||
150 | return SR_OK; | |
151 | } | |
152 | ||
153 | SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi) | |
154 | { | |
155 | struct dev_context *devc; | |
156 | int ret; | |
157 | ||
158 | if (!sdi) | |
159 | return SR_ERR_ARG; | |
160 | devc = sdi->priv; | |
161 | if (!devc) | |
162 | return SR_ERR_ARG; | |
163 | ||
164 | ret = sigma_ftdi_open(sdi); | |
165 | if (ret != SR_OK) | |
166 | return ret; | |
167 | devc->ftdi.must_close = FALSE; | |
168 | ||
169 | return SR_OK; | |
170 | } | |
171 | ||
172 | SR_PRIV int sigma_force_close(struct dev_context *devc) | |
173 | { | |
174 | return sigma_ftdi_close(devc); | |
175 | } | |
176 | ||
88a5f9ea GS |
177 | /* |
178 | * BEWARE! Error propagation is important, as are kinds of return values. | |
179 | * | |
180 | * - Raw USB tranport communicates the number of sent or received bytes, | |
181 | * or negative error codes in the external library's(!) range of codes. | |
182 | * - Internal routines at the "sigrok driver level" communicate success | |
183 | * or failure in terms of SR_OK et al error codes. | |
184 | * - Main loop style receive callbacks communicate booleans which arrange | |
185 | * for repeated calls to drive progress during acquisition. | |
186 | * | |
187 | * Careful consideration by maintainers is essential, because all of the | |
188 | * above kinds of values are assignment compatbile from the compiler's | |
189 | * point of view. Implementation errors will go unnoticed at build time. | |
190 | */ | |
191 | ||
192 | static int sigma_read_raw(struct dev_context *devc, void *buf, size_t size) | |
28a35d8a HE |
193 | { |
194 | int ret; | |
fefa1800 | 195 | |
7fe1f91f | 196 | ret = ftdi_read_data(&devc->ftdi.ctx, (unsigned char *)buf, size); |
28a35d8a | 197 | if (ret < 0) { |
88a5f9ea | 198 | sr_err("USB data read failed: %s", |
7fe1f91f | 199 | ftdi_get_error_string(&devc->ftdi.ctx)); |
28a35d8a HE |
200 | } |
201 | ||
202 | return ret; | |
203 | } | |
204 | ||
88a5f9ea | 205 | static int sigma_write_raw(struct dev_context *devc, const void *buf, size_t size) |
28a35d8a HE |
206 | { |
207 | int ret; | |
fefa1800 | 208 | |
7fe1f91f | 209 | ret = ftdi_write_data(&devc->ftdi.ctx, buf, size); |
88a5f9ea GS |
210 | if (ret < 0) { |
211 | sr_err("USB data write failed: %s", | |
7fe1f91f | 212 | ftdi_get_error_string(&devc->ftdi.ctx)); |
88a5f9ea GS |
213 | } else if ((size_t)ret != size) { |
214 | sr_err("USB data write length mismatch."); | |
215 | } | |
28a35d8a HE |
216 | |
217 | return ret; | |
218 | } | |
219 | ||
88a5f9ea GS |
220 | static int sigma_read_sr(struct dev_context *devc, void *buf, size_t size) |
221 | { | |
222 | int ret; | |
223 | ||
224 | ret = sigma_read_raw(devc, buf, size); | |
225 | if (ret < 0 || (size_t)ret != size) | |
226 | return SR_ERR_IO; | |
227 | ||
228 | return SR_OK; | |
229 | } | |
230 | ||
231 | static int sigma_write_sr(struct dev_context *devc, const void *buf, size_t size) | |
232 | { | |
233 | int ret; | |
234 | ||
235 | ret = sigma_write_raw(devc, buf, size); | |
236 | if (ret < 0 || (size_t)ret != size) | |
237 | return SR_ERR_IO; | |
238 | ||
239 | return SR_OK; | |
240 | } | |
241 | ||
e8686e3a | 242 | /* |
88a5f9ea GS |
243 | * Implementor's note: The local write buffer's size shall suffice for |
244 | * any know FPGA register transaction that is involved in the supported | |
245 | * feature set of this sigrok device driver. If the length check trips, | |
246 | * that's a programmer's error and needs adjustment in the complete call | |
247 | * stack of the respective code path. | |
e8686e3a | 248 | */ |
0f017b7d GS |
249 | #define SIGMA_MAX_REG_DEPTH 32 |
250 | ||
251 | /* | |
252 | * Implementor's note: The FPGA command set supports register access | |
253 | * with automatic address adjustment. This operation is documented to | |
254 | * wrap within a 16-address range, it cannot cross boundaries where the | |
255 | * register address' nibble overflows. An internal helper assumes that | |
256 | * callers remain within this auto-adjustment range, and thus multi | |
257 | * register access requests can never exceed that count. | |
258 | */ | |
259 | #define SIGMA_MAX_REG_COUNT 16 | |
260 | ||
9b4d261f GS |
261 | SR_PRIV int sigma_write_register(struct dev_context *devc, |
262 | uint8_t reg, uint8_t *data, size_t len) | |
28a35d8a | 263 | { |
0f017b7d | 264 | uint8_t buf[2 + SIGMA_MAX_REG_DEPTH * 2], *wrptr; |
88a5f9ea | 265 | size_t idx; |
28a35d8a | 266 | |
0f017b7d | 267 | if (len > SIGMA_MAX_REG_DEPTH) { |
88a5f9ea | 268 | sr_err("Short write buffer for %zu bytes to reg %u.", len, reg); |
e8686e3a AG |
269 | return SR_ERR_BUG; |
270 | } | |
271 | ||
a53b8e4d | 272 | wrptr = buf; |
0f017b7d GS |
273 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg)); |
274 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg)); | |
a53b8e4d | 275 | for (idx = 0; idx < len; idx++) { |
0f017b7d GS |
276 | write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data[idx])); |
277 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data[idx])); | |
28a35d8a HE |
278 | } |
279 | ||
88a5f9ea | 280 | return sigma_write_sr(devc, buf, wrptr - buf); |
28a35d8a HE |
281 | } |
282 | ||
9b4d261f GS |
283 | SR_PRIV int sigma_set_register(struct dev_context *devc, |
284 | uint8_t reg, uint8_t value) | |
28a35d8a | 285 | { |
9b4d261f | 286 | return sigma_write_register(devc, reg, &value, sizeof(value)); |
28a35d8a HE |
287 | } |
288 | ||
9b4d261f GS |
289 | static int sigma_read_register(struct dev_context *devc, |
290 | uint8_t reg, uint8_t *data, size_t len) | |
28a35d8a | 291 | { |
a53b8e4d | 292 | uint8_t buf[3], *wrptr; |
88a5f9ea | 293 | int ret; |
28a35d8a | 294 | |
a53b8e4d | 295 | wrptr = buf; |
0f017b7d GS |
296 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg)); |
297 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg)); | |
a53b8e4d | 298 | write_u8_inc(&wrptr, REG_READ_ADDR); |
88a5f9ea GS |
299 | ret = sigma_write_sr(devc, buf, wrptr - buf); |
300 | if (ret != SR_OK) | |
301 | return ret; | |
28a35d8a | 302 | |
88a5f9ea | 303 | return sigma_read_sr(devc, data, len); |
28a35d8a HE |
304 | } |
305 | ||
0f017b7d GS |
306 | static int sigma_get_register(struct dev_context *devc, |
307 | uint8_t reg, uint8_t *data) | |
308 | { | |
309 | return sigma_read_register(devc, reg, data, sizeof(*data)); | |
310 | } | |
311 | ||
312 | static int sigma_get_registers(struct dev_context *devc, | |
313 | uint8_t reg, uint8_t *data, size_t count) | |
314 | { | |
315 | uint8_t buf[2 + SIGMA_MAX_REG_COUNT], *wrptr; | |
316 | size_t idx; | |
317 | int ret; | |
318 | ||
319 | if (count > SIGMA_MAX_REG_COUNT) { | |
320 | sr_err("Short command buffer for %zu reg reads at %u.", count, reg); | |
321 | return SR_ERR_BUG; | |
322 | } | |
323 | ||
324 | wrptr = buf; | |
325 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg)); | |
326 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg)); | |
327 | for (idx = 0; idx < count; idx++) | |
328 | write_u8_inc(&wrptr, REG_READ_ADDR | REG_ADDR_INC); | |
329 | ret = sigma_write_sr(devc, buf, wrptr - buf); | |
330 | if (ret != SR_OK) | |
331 | return ret; | |
332 | ||
333 | return sigma_read_sr(devc, data, count); | |
334 | } | |
335 | ||
9b4d261f | 336 | static int sigma_read_pos(struct dev_context *devc, |
88a5f9ea | 337 | uint32_t *stoppos, uint32_t *triggerpos, uint8_t *mode) |
28a35d8a | 338 | { |
88a5f9ea | 339 | uint8_t result[7]; |
0f017b7d | 340 | const uint8_t *rdptr; |
88a5f9ea GS |
341 | uint32_t v32; |
342 | uint8_t v8; | |
343 | int ret; | |
28a35d8a | 344 | |
0f017b7d GS |
345 | /* |
346 | * Read 7 registers starting at trigger position LSB. | |
347 | * Which yields two 24bit counter values, and mode flags. | |
348 | */ | |
349 | ret = sigma_get_registers(devc, READ_TRIGGER_POS_LOW, | |
350 | result, sizeof(result)); | |
88a5f9ea GS |
351 | if (ret != SR_OK) |
352 | return ret; | |
28a35d8a | 353 | |
a53b8e4d | 354 | rdptr = &result[0]; |
88a5f9ea GS |
355 | v32 = read_u24le_inc(&rdptr); |
356 | if (triggerpos) | |
357 | *triggerpos = v32; | |
358 | v32 = read_u24le_inc(&rdptr); | |
359 | if (stoppos) | |
360 | *stoppos = v32; | |
361 | v8 = read_u8_inc(&rdptr); | |
362 | if (mode) | |
363 | *mode = v8; | |
28a35d8a | 364 | |
dc400817 | 365 | /* |
a53b8e4d GS |
366 | * These positions consist of "the memory row" in the MSB fields, |
367 | * and "an event index" within the row in the LSB fields. Part | |
368 | * of the memory row's content is sample data, another part is | |
369 | * timestamps. | |
2c33b092 | 370 | * |
a53b8e4d GS |
371 | * The retrieved register values point to after the captured |
372 | * position. So they need to get decremented, and adjusted to | |
373 | * cater for the timestamps when the decrement carries over to | |
374 | * a different memory row. | |
dc400817 | 375 | */ |
88a5f9ea | 376 | if (stoppos && (--*stoppos & ROW_MASK) == ROW_MASK) |
a53b8e4d | 377 | *stoppos -= CLUSTERS_PER_ROW; |
88a5f9ea | 378 | if (triggerpos && (--*triggerpos & ROW_MASK) == ROW_MASK) |
a53b8e4d | 379 | *triggerpos -= CLUSTERS_PER_ROW; |
57bbf56b | 380 | |
a53b8e4d | 381 | return SR_OK; |
28a35d8a HE |
382 | } |
383 | ||
9b4d261f | 384 | static int sigma_read_dram(struct dev_context *devc, |
3d9373af | 385 | size_t startchunk, size_t numchunks, uint8_t *data) |
28a35d8a | 386 | { |
0f017b7d | 387 | uint8_t buf[128], *wrptr, regval; |
07411a60 | 388 | size_t chunk; |
88a5f9ea | 389 | int sel, ret; |
07411a60 | 390 | gboolean is_last; |
28a35d8a | 391 | |
a53b8e4d | 392 | if (2 + 3 * numchunks > ARRAY_SIZE(buf)) { |
88a5f9ea | 393 | sr_err("Short write buffer for %zu DRAM row reads.", numchunks); |
a53b8e4d GS |
394 | return SR_ERR_BUG; |
395 | } | |
396 | ||
07411a60 | 397 | /* Communicate DRAM start address (memory row, aka samples line). */ |
a53b8e4d | 398 | wrptr = buf; |
0f017b7d | 399 | write_u16be_inc(&wrptr, startchunk); |
88a5f9ea GS |
400 | ret = sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf); |
401 | if (ret != SR_OK) | |
402 | return ret; | |
28a35d8a | 403 | |
07411a60 GS |
404 | /* |
405 | * Access DRAM content. Fetch from DRAM to FPGA's internal RAM, | |
406 | * then transfer via USB. Interleave the FPGA's DRAM access and | |
407 | * USB transfer, use alternating buffers (0/1) in the process. | |
408 | */ | |
a53b8e4d GS |
409 | wrptr = buf; |
410 | write_u8_inc(&wrptr, REG_DRAM_BLOCK); | |
411 | write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK); | |
07411a60 GS |
412 | for (chunk = 0; chunk < numchunks; chunk++) { |
413 | sel = chunk % 2; | |
414 | is_last = chunk == numchunks - 1; | |
0f017b7d GS |
415 | if (!is_last) { |
416 | regval = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel); | |
417 | write_u8_inc(&wrptr, regval); | |
418 | } | |
419 | regval = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel); | |
420 | write_u8_inc(&wrptr, regval); | |
07411a60 | 421 | if (!is_last) |
a53b8e4d | 422 | write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK); |
28a35d8a | 423 | } |
88a5f9ea GS |
424 | ret = sigma_write_sr(devc, buf, wrptr - buf); |
425 | if (ret != SR_OK) | |
426 | return ret; | |
28a35d8a | 427 | |
88a5f9ea | 428 | return sigma_read_sr(devc, data, numchunks * ROW_LENGTH_BYTES); |
28a35d8a HE |
429 | } |
430 | ||
4ae1f451 | 431 | /* Upload trigger look-up tables to Sigma. */ |
9b4d261f GS |
432 | SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, |
433 | struct triggerlut *lut) | |
ee492173 | 434 | { |
3d9373af | 435 | size_t lut_addr; |
ee492173 | 436 | uint16_t bit; |
72ea3b84 | 437 | uint8_t m3d, m2d, m1d, m0d; |
3d9373af | 438 | uint8_t buf[6], *wrptr, v8; |
16791da9 | 439 | uint16_t selreg; |
88a5f9ea | 440 | int ret; |
ee492173 | 441 | |
72ea3b84 GS |
442 | /* |
443 | * Translate the LUT part of the trigger configuration from the | |
444 | * application's perspective to the hardware register's bitfield | |
445 | * layout. Send the LUT to the device. This configures the logic | |
446 | * which combines pin levels or edges. | |
447 | */ | |
0f017b7d GS |
448 | for (lut_addr = 0; lut_addr < 16; lut_addr++) { |
449 | bit = 1 << lut_addr; | |
ee492173 | 450 | |
72ea3b84 GS |
451 | /* - M4 M3S M3Q */ |
452 | m3d = 0; | |
453 | if (lut->m4 & bit) | |
454 | m3d |= 1 << 2; | |
455 | if (lut->m3s & bit) | |
456 | m3d |= 1 << 1; | |
16791da9 | 457 | if (lut->m3q & bit) |
72ea3b84 | 458 | m3d |= 1 << 0; |
ee492173 | 459 | |
72ea3b84 GS |
460 | /* M2D3 M2D2 M2D1 M2D0 */ |
461 | m2d = 0; | |
ee492173 | 462 | if (lut->m2d[3] & bit) |
72ea3b84 GS |
463 | m2d |= 1 << 3; |
464 | if (lut->m2d[2] & bit) | |
465 | m2d |= 1 << 2; | |
466 | if (lut->m2d[1] & bit) | |
467 | m2d |= 1 << 1; | |
468 | if (lut->m2d[0] & bit) | |
469 | m2d |= 1 << 0; | |
ee492173 | 470 | |
72ea3b84 GS |
471 | /* M1D3 M1D2 M1D1 M1D0 */ |
472 | m1d = 0; | |
473 | if (lut->m1d[3] & bit) | |
474 | m1d |= 1 << 3; | |
475 | if (lut->m1d[2] & bit) | |
476 | m1d |= 1 << 2; | |
477 | if (lut->m1d[1] & bit) | |
478 | m1d |= 1 << 1; | |
479 | if (lut->m1d[0] & bit) | |
480 | m1d |= 1 << 0; | |
ee492173 | 481 | |
72ea3b84 GS |
482 | /* M0D3 M0D2 M0D1 M0D0 */ |
483 | m0d = 0; | |
ee492173 | 484 | if (lut->m0d[3] & bit) |
72ea3b84 GS |
485 | m0d |= 1 << 3; |
486 | if (lut->m0d[2] & bit) | |
487 | m0d |= 1 << 2; | |
488 | if (lut->m0d[1] & bit) | |
489 | m0d |= 1 << 1; | |
490 | if (lut->m0d[0] & bit) | |
491 | m0d |= 1 << 0; | |
ee492173 | 492 | |
a53b8e4d | 493 | /* |
72ea3b84 GS |
494 | * Send 16bits with M3D/M2D and M1D/M0D bit masks to the |
495 | * TriggerSelect register, then strobe the LUT write by | |
496 | * passing A3-A0 to TriggerSelect2. Hold RESET during LUT | |
497 | * programming. | |
a53b8e4d GS |
498 | */ |
499 | wrptr = buf; | |
72ea3b84 GS |
500 | write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0)); |
501 | write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0)); | |
419f1095 GS |
502 | ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, |
503 | buf, wrptr - buf); | |
88a5f9ea GS |
504 | if (ret != SR_OK) |
505 | return ret; | |
3d9373af GS |
506 | v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE | |
507 | (lut_addr & TRGSEL2_LUT_ADDR_MASK); | |
508 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8); | |
88a5f9ea GS |
509 | if (ret != SR_OK) |
510 | return ret; | |
ee492173 HE |
511 | } |
512 | ||
72ea3b84 GS |
513 | /* |
514 | * Send the parameters. This covers counters and durations. | |
515 | */ | |
a53b8e4d | 516 | wrptr = buf; |
16791da9 GS |
517 | selreg = 0; |
518 | selreg |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT; | |
519 | selreg |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT; | |
520 | selreg |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT; | |
521 | selreg |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT; | |
522 | selreg |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT; | |
523 | selreg |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT; | |
524 | write_u16be_inc(&wrptr, selreg); | |
0f017b7d GS |
525 | write_u16be_inc(&wrptr, lut->params.cmpb); |
526 | write_u16be_inc(&wrptr, lut->params.cmpa); | |
88a5f9ea GS |
527 | ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); |
528 | if (ret != SR_OK) | |
529 | return ret; | |
ee492173 | 530 | |
e46b8fb1 | 531 | return SR_OK; |
ee492173 HE |
532 | } |
533 | ||
d5fa188a | 534 | /* |
dc0906e2 GS |
535 | * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device |
536 | * uses FTDI bitbang mode for netlist download in slave serial mode. | |
537 | * (LATER: The OMEGA device's cable contains a more capable FTDI chip | |
538 | * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245 | |
539 | * compatible bitbang mode? For maximum code re-use and reduced libftdi | |
540 | * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2 | |
541 | * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.) | |
542 | * | |
543 | * 750kbps rate (four times the speed of sigmalogan) works well for | |
544 | * netlist download. All pins except INIT_B are output pins during | |
545 | * configuration download. | |
546 | * | |
547 | * Some pins are inverted as a byproduct of level shifting circuitry. | |
548 | * That's why high CCLK level (from the cable's point of view) is idle | |
549 | * from the FPGA's perspective. | |
550 | * | |
551 | * The vendor's literature discusses a "suicide sequence" which ends | |
552 | * regular FPGA execution and should be sent before entering bitbang | |
553 | * mode and sending configuration data. Set D7 and toggle D2, D3, D4 | |
554 | * a few times. | |
555 | */ | |
556 | #define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ | |
557 | #define BB_PIN_PROG (1 << 1) /* D1, PROG */ | |
558 | #define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ | |
559 | #define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ | |
560 | #define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ | |
561 | #define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ | |
562 | #define BB_PIN_DIN (1 << 6) /* D6, DIN */ | |
563 | #define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ | |
564 | ||
565 | #define BB_BITRATE (750 * 1000) | |
566 | #define BB_PINMASK (0xff & ~BB_PIN_INIT) | |
567 | ||
568 | /* | |
569 | * Initiate slave serial mode for configuration download. Which is done | |
570 | * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before | |
c749d1ca GS |
571 | * initiating the configuration download. |
572 | * | |
573 | * Run a "suicide sequence" first to terminate the regular FPGA operation | |
574 | * before reconfiguration. The FTDI cable is single channel, and shares | |
575 | * pins which are used for data communication in FIFO mode with pins that | |
576 | * are used for FPGA configuration in bitbang mode. Hardware defaults for | |
577 | * unconfigured hardware, and runtime conditions after FPGA configuration | |
578 | * need to cooperate such that re-configuration of the FPGA can start. | |
d5fa188a | 579 | */ |
c749d1ca | 580 | static int sigma_fpga_init_bitbang_once(struct dev_context *devc) |
d5fa188a | 581 | { |
a53b8e4d | 582 | const uint8_t suicide[] = { |
dc0906e2 GS |
583 | BB_PIN_D7 | BB_PIN_D2, |
584 | BB_PIN_D7 | BB_PIN_D2, | |
585 | BB_PIN_D7 | BB_PIN_D3, | |
586 | BB_PIN_D7 | BB_PIN_D2, | |
587 | BB_PIN_D7 | BB_PIN_D3, | |
588 | BB_PIN_D7 | BB_PIN_D2, | |
589 | BB_PIN_D7 | BB_PIN_D3, | |
590 | BB_PIN_D7 | BB_PIN_D2, | |
d5fa188a | 591 | }; |
a53b8e4d | 592 | const uint8_t init_array[] = { |
dc0906e2 GS |
593 | BB_PIN_CCLK, |
594 | BB_PIN_CCLK | BB_PIN_PROG, | |
595 | BB_PIN_CCLK | BB_PIN_PROG, | |
596 | BB_PIN_CCLK, | |
597 | BB_PIN_CCLK, | |
598 | BB_PIN_CCLK, | |
599 | BB_PIN_CCLK, | |
600 | BB_PIN_CCLK, | |
601 | BB_PIN_CCLK, | |
602 | BB_PIN_CCLK, | |
d5fa188a | 603 | }; |
3d9373af GS |
604 | size_t retries; |
605 | int ret; | |
d5fa188a MV |
606 | uint8_t data; |
607 | ||
608 | /* Section 2. part 1), do the FPGA suicide. */ | |
88a5f9ea GS |
609 | ret = SR_OK; |
610 | ret |= sigma_write_sr(devc, suicide, sizeof(suicide)); | |
611 | ret |= sigma_write_sr(devc, suicide, sizeof(suicide)); | |
612 | ret |= sigma_write_sr(devc, suicide, sizeof(suicide)); | |
613 | ret |= sigma_write_sr(devc, suicide, sizeof(suicide)); | |
614 | if (ret != SR_OK) | |
615 | return SR_ERR_IO; | |
c749d1ca | 616 | g_usleep(10 * 1000); |
d5fa188a | 617 | |
dc0906e2 | 618 | /* Section 2. part 2), pulse PROG. */ |
88a5f9ea GS |
619 | ret = sigma_write_sr(devc, init_array, sizeof(init_array)); |
620 | if (ret != SR_OK) | |
621 | return ret; | |
c749d1ca | 622 | g_usleep(10 * 1000); |
7fe1f91f | 623 | ftdi_usb_purge_buffers(&devc->ftdi.ctx); |
d5fa188a | 624 | |
88a5f9ea GS |
625 | /* |
626 | * Wait until the FPGA asserts INIT_B. Check in a maximum number | |
627 | * of bursts with a given delay between them. Read as many pin | |
628 | * capture results as the combination of FTDI chip and FTID lib | |
629 | * may provide. Cope with absence of pin capture data in a cycle. | |
630 | * This approach shall result in fast reponse in case of success, | |
631 | * low cost of execution during wait, reliable error handling in | |
632 | * the transport layer, and robust response to failure or absence | |
633 | * of result data (hardware inactivity after stimulus). | |
634 | */ | |
dc0906e2 GS |
635 | retries = 10; |
636 | while (retries--) { | |
88a5f9ea GS |
637 | do { |
638 | ret = sigma_read_raw(devc, &data, sizeof(data)); | |
639 | if (ret < 0) | |
640 | return SR_ERR_IO; | |
641 | if (ret == sizeof(data) && (data & BB_PIN_INIT)) | |
642 | return SR_OK; | |
643 | } while (ret == sizeof(data)); | |
644 | if (retries) | |
645 | g_usleep(10 * 1000); | |
d5fa188a MV |
646 | } |
647 | ||
648 | return SR_ERR_TIMEOUT; | |
649 | } | |
650 | ||
c749d1ca GS |
651 | /* |
652 | * This is belt and braces. Re-run the bitbang initiation sequence a few | |
653 | * times should first attempts fail. Failure is rare but can happen (was | |
654 | * observed during driver development). | |
655 | */ | |
656 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
657 | { | |
658 | size_t retries; | |
659 | int ret; | |
660 | ||
661 | retries = 10; | |
662 | while (retries--) { | |
663 | ret = sigma_fpga_init_bitbang_once(devc); | |
664 | if (ret == SR_OK) | |
665 | return ret; | |
666 | if (ret != SR_ERR_TIMEOUT) | |
667 | return ret; | |
668 | } | |
669 | return ret; | |
670 | } | |
671 | ||
64fe661b MV |
672 | /* |
673 | * Configure the FPGA for logic-analyzer mode. | |
674 | */ | |
675 | static int sigma_fpga_init_la(struct dev_context *devc) | |
676 | { | |
0f017b7d | 677 | uint8_t buf[20], *wrptr; |
a53b8e4d | 678 | uint8_t data_55, data_aa, mode; |
64fe661b | 679 | uint8_t result[3]; |
a53b8e4d | 680 | const uint8_t *rdptr; |
64fe661b MV |
681 | int ret; |
682 | ||
a53b8e4d GS |
683 | wrptr = buf; |
684 | ||
685 | /* Read ID register. */ | |
0f017b7d GS |
686 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(READ_ID)); |
687 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(READ_ID)); | |
a53b8e4d GS |
688 | write_u8_inc(&wrptr, REG_READ_ADDR); |
689 | ||
690 | /* Write 0x55 to scratch register, read back. */ | |
691 | data_55 = 0x55; | |
0f017b7d GS |
692 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST)); |
693 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST)); | |
694 | write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_55)); | |
695 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_55)); | |
a53b8e4d GS |
696 | write_u8_inc(&wrptr, REG_READ_ADDR); |
697 | ||
698 | /* Write 0xaa to scratch register, read back. */ | |
699 | data_aa = 0xaa; | |
0f017b7d GS |
700 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST)); |
701 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST)); | |
702 | write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_aa)); | |
703 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_aa)); | |
a53b8e4d GS |
704 | write_u8_inc(&wrptr, REG_READ_ADDR); |
705 | ||
706 | /* Initiate SDRAM initialization in mode register. */ | |
707 | mode = WMR_SDRAMINIT; | |
0f017b7d GS |
708 | write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_MODE)); |
709 | write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_MODE)); | |
710 | write_u8_inc(&wrptr, REG_DATA_LOW | LO4(mode)); | |
711 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(mode)); | |
a53b8e4d | 712 | |
dc0906e2 GS |
713 | /* |
714 | * Send the command sequence which contains 3 READ requests. | |
715 | * Expect to see the corresponding 3 response bytes. | |
716 | */ | |
88a5f9ea GS |
717 | ret = sigma_write_sr(devc, buf, wrptr - buf); |
718 | if (ret != SR_OK) { | |
719 | sr_err("Could not request LA start response."); | |
720 | return ret; | |
721 | } | |
722 | ret = sigma_read_sr(devc, result, ARRAY_SIZE(result)); | |
723 | if (ret != SR_OK) { | |
724 | sr_err("Could not receive LA start response."); | |
a53b8e4d GS |
725 | return SR_ERR_IO; |
726 | } | |
727 | rdptr = result; | |
728 | if (read_u8_inc(&rdptr) != 0xa6) { | |
729 | sr_err("Unexpected ID response."); | |
730 | return SR_ERR_DATA; | |
731 | } | |
732 | if (read_u8_inc(&rdptr) != data_55) { | |
733 | sr_err("Unexpected scratch read-back (55)."); | |
734 | return SR_ERR_DATA; | |
735 | } | |
736 | if (read_u8_inc(&rdptr) != data_aa) { | |
737 | sr_err("Unexpected scratch read-back (aa)."); | |
738 | return SR_ERR_DATA; | |
739 | } | |
64fe661b MV |
740 | |
741 | return SR_OK; | |
64fe661b MV |
742 | } |
743 | ||
a80226bb MV |
744 | /* |
745 | * Read the firmware from a file and transform it into a series of bitbang | |
746 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
747 | * by the caller of this function. | |
748 | */ | |
8e2d6c9d | 749 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
3d9373af | 750 | uint8_t **bb_cmd, size_t *bb_cmd_size) |
a80226bb | 751 | { |
dc0906e2 GS |
752 | uint8_t *firmware; |
753 | size_t file_size; | |
754 | uint8_t *p; | |
755 | size_t l; | |
a80226bb | 756 | uint32_t imm; |
dc0906e2 GS |
757 | size_t bb_size; |
758 | uint8_t *bb_stream, *bbs, byte, mask, v; | |
a80226bb | 759 | |
387825dc | 760 | /* Retrieve the on-disk firmware file content. */ |
742368a2 GS |
761 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name, |
762 | &file_size, SIGMA_FIRMWARE_SIZE_LIMIT); | |
8e2d6c9d | 763 | if (!firmware) |
dc0906e2 | 764 | return SR_ERR_IO; |
a80226bb | 765 | |
387825dc | 766 | /* Unscramble the file content (XOR with "random" sequence). */ |
dc0906e2 GS |
767 | p = firmware; |
768 | l = file_size; | |
a80226bb | 769 | imm = 0x3f6df2ab; |
dc0906e2 | 770 | while (l--) { |
a80226bb | 771 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); |
dc0906e2 | 772 | *p++ ^= imm & 0xff; |
a80226bb MV |
773 | } |
774 | ||
775 | /* | |
387825dc GS |
776 | * Generate a sequence of bitbang samples. With two samples per |
777 | * FPGA configuration bit, providing the level for the DIN signal | |
778 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
779 | * ("slave serial" mode). | |
780 | * | |
781 | * Note that CCLK is inverted in hardware. That's why the | |
782 | * respective bit is first set and then cleared in the bitbang | |
783 | * sample sets. So that the DIN level will be stable when the | |
784 | * data gets sampled at the rising CCLK edge, and the signals' | |
785 | * setup time constraint will be met. | |
786 | * | |
787 | * The caller will put the FPGA into download mode, will send | |
788 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 789 | */ |
a80226bb | 790 | bb_size = file_size * 8 * 2; |
dc0906e2 | 791 | bb_stream = g_try_malloc(bb_size); |
a80226bb | 792 | if (!bb_stream) { |
88a5f9ea | 793 | sr_err("Memory allocation failed during firmware upload."); |
dc0906e2 GS |
794 | g_free(firmware); |
795 | return SR_ERR_MALLOC; | |
a80226bb | 796 | } |
a80226bb | 797 | bbs = bb_stream; |
dc0906e2 GS |
798 | p = firmware; |
799 | l = file_size; | |
800 | while (l--) { | |
801 | byte = *p++; | |
802 | mask = 0x80; | |
803 | while (mask) { | |
804 | v = (byte & mask) ? BB_PIN_DIN : 0; | |
805 | mask >>= 1; | |
806 | *bbs++ = v | BB_PIN_CCLK; | |
a80226bb MV |
807 | *bbs++ = v; |
808 | } | |
809 | } | |
dc0906e2 | 810 | g_free(firmware); |
a80226bb MV |
811 | |
812 | /* The transformation completed successfully, return the result. */ | |
813 | *bb_cmd = bb_stream; | |
814 | *bb_cmd_size = bb_size; | |
815 | ||
dc0906e2 | 816 | return SR_OK; |
a80226bb MV |
817 | } |
818 | ||
9b4d261f GS |
819 | static int upload_firmware(struct sr_context *ctx, struct dev_context *devc, |
820 | enum sigma_firmware_idx firmware_idx) | |
28a35d8a HE |
821 | { |
822 | int ret; | |
a53b8e4d GS |
823 | uint8_t *buf; |
824 | uint8_t pins; | |
28a35d8a | 825 | size_t buf_size; |
a9016883 | 826 | const char *firmware; |
a9016883 | 827 | |
80e717b3 GS |
828 | /* Check for valid firmware file selection. */ |
829 | if (firmware_idx >= ARRAY_SIZE(firmware_files)) | |
830 | return SR_ERR_ARG; | |
4b25cbff | 831 | firmware = firmware_files[firmware_idx]; |
80e717b3 GS |
832 | if (!firmware || !*firmware) |
833 | return SR_ERR_ARG; | |
834 | ||
835 | /* Avoid downloading the same firmware multiple times. */ | |
836 | if (devc->firmware_idx == firmware_idx) { | |
a9016883 GS |
837 | sr_info("Not uploading firmware file '%s' again.", firmware); |
838 | return SR_OK; | |
839 | } | |
28a35d8a | 840 | |
1bb9dc82 GS |
841 | devc->state.state = SIGMA_CONFIG; |
842 | ||
dc0906e2 | 843 | /* Set the cable to bitbang mode. */ |
7fe1f91f | 844 | ret = ftdi_set_bitmode(&devc->ftdi.ctx, BB_PINMASK, BITMODE_BITBANG); |
8bbf7627 | 845 | if (ret < 0) { |
88a5f9ea | 846 | sr_err("Could not setup cable mode for upload: %s", |
7fe1f91f | 847 | ftdi_get_error_string(&devc->ftdi.ctx)); |
7bcf2168 | 848 | return SR_ERR; |
28a35d8a | 849 | } |
7fe1f91f | 850 | ret = ftdi_set_baudrate(&devc->ftdi.ctx, BB_BITRATE); |
8bbf7627 | 851 | if (ret < 0) { |
88a5f9ea | 852 | sr_err("Could not setup bitrate for upload: %s", |
7fe1f91f | 853 | ftdi_get_error_string(&devc->ftdi.ctx)); |
7bcf2168 | 854 | return SR_ERR; |
28a35d8a HE |
855 | } |
856 | ||
dc0906e2 | 857 | /* Initiate FPGA configuration mode. */ |
d5fa188a | 858 | ret = sigma_fpga_init_bitbang(devc); |
88a5f9ea GS |
859 | if (ret) { |
860 | sr_err("Could not initiate firmware upload to hardware"); | |
d5fa188a | 861 | return ret; |
88a5f9ea | 862 | } |
28a35d8a | 863 | |
dc0906e2 | 864 | /* Prepare wire format of the firmware image. */ |
8e2d6c9d | 865 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 866 | if (ret != SR_OK) { |
88a5f9ea | 867 | sr_err("Could not prepare file %s for upload.", firmware); |
b53738ba | 868 | return ret; |
28a35d8a HE |
869 | } |
870 | ||
dc0906e2 | 871 | /* Write the FPGA netlist to the cable. */ |
499b17e9 | 872 | sr_info("Uploading firmware file '%s'.", firmware); |
88a5f9ea | 873 | ret = sigma_write_sr(devc, buf, buf_size); |
28a35d8a | 874 | g_free(buf); |
88a5f9ea GS |
875 | if (ret != SR_OK) { |
876 | sr_err("Could not upload firmware file '%s'.", firmware); | |
877 | return ret; | |
878 | } | |
28a35d8a | 879 | |
dc0906e2 | 880 | /* Leave bitbang mode and discard pending input data. */ |
7fe1f91f | 881 | ret = ftdi_set_bitmode(&devc->ftdi.ctx, 0, BITMODE_RESET); |
8bbf7627 | 882 | if (ret < 0) { |
88a5f9ea | 883 | sr_err("Could not setup cable mode after upload: %s", |
7fe1f91f | 884 | ftdi_get_error_string(&devc->ftdi.ctx)); |
e46b8fb1 | 885 | return SR_ERR; |
28a35d8a | 886 | } |
7fe1f91f | 887 | ftdi_usb_purge_buffers(&devc->ftdi.ctx); |
88a5f9ea | 888 | while (sigma_read_raw(devc, &pins, sizeof(pins)) > 0) |
28a35d8a HE |
889 | ; |
890 | ||
64fe661b MV |
891 | /* Initialize the FPGA for logic-analyzer mode. */ |
892 | ret = sigma_fpga_init_la(devc); | |
88a5f9ea GS |
893 | if (ret != SR_OK) { |
894 | sr_err("Hardware response after firmware upload failed."); | |
64fe661b | 895 | return ret; |
88a5f9ea | 896 | } |
28a35d8a | 897 | |
dc0906e2 | 898 | /* Keep track of successful firmware download completion. */ |
1bb9dc82 | 899 | devc->state.state = SIGMA_IDLE; |
80e717b3 | 900 | devc->firmware_idx = firmware_idx; |
47f4f073 | 901 | sr_info("Firmware uploaded."); |
e3fff420 | 902 | |
e46b8fb1 | 903 | return SR_OK; |
f6564c8d HE |
904 | } |
905 | ||
9a0a606a | 906 | /* |
5e78a564 GS |
907 | * The driver supports user specified time or sample count limits. The |
908 | * device's hardware supports neither, and hardware compression prevents | |
909 | * reliable detection of "fill levels" (currently reached sample counts) | |
910 | * from register values during acquisition. That's why the driver needs | |
911 | * to apply some heuristics: | |
9a0a606a | 912 | * |
5e78a564 GS |
913 | * - The (optional) sample count limit and the (normalized) samplerate |
914 | * get mapped to an estimated duration for these samples' acquisition. | |
915 | * - The (optional) time limit gets checked as well. The lesser of the | |
916 | * two limits will terminate the data acquisition phase. The exact | |
917 | * sample count limit gets enforced in session feed submission paths. | |
918 | * - Some slack needs to be given to account for hardware pipelines as | |
919 | * well as late storage of last chunks after compression thresholds | |
920 | * are tripped. The resulting data set will span at least the caller | |
921 | * specified period of time, which shall be perfectly acceptable. | |
922 | * | |
923 | * With RLE compression active, up to 64K sample periods can pass before | |
924 | * a cluster accumulates. Which translates to 327ms at 200kHz. Add two | |
925 | * times that period for good measure, one is not enough to flush the | |
926 | * hardware pipeline (observation from an earlier experiment). | |
9a0a606a | 927 | */ |
5e78a564 | 928 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) |
9a0a606a | 929 | { |
5e78a564 GS |
930 | int ret; |
931 | GVariant *data; | |
932 | uint64_t user_count, user_msecs; | |
9a0a606a | 933 | uint64_t worst_cluster_time_ms; |
5e78a564 | 934 | uint64_t count_msecs, acquire_msecs; |
9a0a606a | 935 | |
5e78a564 GS |
936 | sr_sw_limits_init(&devc->acq_limits); |
937 | ||
938 | /* Get sample count limit, convert to msecs. */ | |
939 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
940 | SR_CONF_LIMIT_SAMPLES, &data); | |
941 | if (ret != SR_OK) | |
942 | return ret; | |
943 | user_count = g_variant_get_uint64(data); | |
944 | g_variant_unref(data); | |
945 | count_msecs = 0; | |
946 | if (user_count) | |
2d8a5089 | 947 | count_msecs = 1000 * user_count / devc->clock.samplerate + 1; |
5e78a564 GS |
948 | |
949 | /* Get time limit, which is in msecs. */ | |
950 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
951 | SR_CONF_LIMIT_MSEC, &data); | |
952 | if (ret != SR_OK) | |
953 | return ret; | |
954 | user_msecs = g_variant_get_uint64(data); | |
955 | g_variant_unref(data); | |
956 | ||
957 | /* Get the lesser of them, with both being optional. */ | |
958 | acquire_msecs = ~0ull; | |
959 | if (user_count && count_msecs < acquire_msecs) | |
960 | acquire_msecs = count_msecs; | |
961 | if (user_msecs && user_msecs < acquire_msecs) | |
962 | acquire_msecs = user_msecs; | |
963 | if (acquire_msecs == ~0ull) | |
964 | return SR_OK; | |
965 | ||
966 | /* Add some slack, and use that timeout for acquisition. */ | |
2d8a5089 | 967 | worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate; |
5e78a564 GS |
968 | acquire_msecs += 2 * worst_cluster_time_ms; |
969 | data = g_variant_new_uint64(acquire_msecs); | |
970 | ret = sr_sw_limits_config_set(&devc->acq_limits, | |
971 | SR_CONF_LIMIT_MSEC, data); | |
972 | g_variant_unref(data); | |
973 | if (ret != SR_OK) | |
974 | return ret; | |
975 | ||
976 | sr_sw_limits_acquisition_start(&devc->acq_limits); | |
977 | return SR_OK; | |
9a0a606a GS |
978 | } |
979 | ||
5e78a564 GS |
980 | /* |
981 | * Check whether a caller specified samplerate matches the device's | |
982 | * hardware constraints (can be used for acquisition). Optionally yield | |
983 | * a value that approximates the original spec. | |
984 | * | |
985 | * This routine assumes that input specs are in the 200kHz to 200MHz | |
986 | * range of supported rates, and callers typically want to normalize a | |
987 | * given value to the hardware capabilities. Values in the 50MHz range | |
988 | * get rounded up by default, to avoid a more expensive check for the | |
989 | * closest match, while higher sampling rate is always desirable during | |
990 | * measurement. Input specs which exactly match hardware capabilities | |
991 | * remain unaffected. Because 100/200MHz rates also limit the number of | |
992 | * available channels, they are not suggested by this routine, instead | |
993 | * callers need to pick them consciously. | |
994 | */ | |
995 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate) | |
996 | { | |
997 | uint64_t div, rate; | |
998 | ||
999 | /* Accept exact matches for 100/200MHz. */ | |
1000 | if (want_rate == SR_MHZ(200) || want_rate == SR_MHZ(100)) { | |
1001 | if (have_rate) | |
1002 | *have_rate = want_rate; | |
1003 | return SR_OK; | |
1004 | } | |
1005 | ||
1006 | /* Accept 200kHz to 50MHz range, and map to near value. */ | |
1007 | if (want_rate >= SR_KHZ(200) && want_rate <= SR_MHZ(50)) { | |
1008 | div = SR_MHZ(50) / want_rate; | |
1009 | rate = SR_MHZ(50) / div; | |
1010 | if (have_rate) | |
1011 | *have_rate = rate; | |
1012 | return SR_OK; | |
1013 | } | |
1014 | ||
1015 | return SR_ERR_ARG; | |
1016 | } | |
1017 | ||
53c8a99c GS |
1018 | /* Gets called at probe time. Can seed software settings from hardware state. */ |
1019 | SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi) | |
abcd4771 | 1020 | { |
53c8a99c GS |
1021 | struct dev_context *devc; |
1022 | int ret; | |
1023 | uint8_t regaddr, regval; | |
1024 | ||
1025 | devc = sdi->priv; | |
1026 | if (!devc) | |
1027 | return SR_ERR_ARG; | |
1028 | ||
1029 | /* Seed configuration values from defaults. */ | |
1030 | devc->firmware_idx = SIGMA_FW_NONE; | |
1031 | devc->clock.samplerate = samplerates[0]; | |
1032 | ||
1033 | /* TODO | |
1034 | * Ideally the device driver could retrieve recently stored | |
1035 | * details from hardware registers, thus re-use user specified | |
1036 | * configuration values across sigrok sessions. Which could | |
1037 | * avoid repeated expensive though unnecessary firmware uploads, | |
1038 | * improve performance and usability. Unfortunately it appears | |
1039 | * that the registers range which is documented as available for | |
1040 | * application use keeps providing 0xff data content. At least | |
1041 | * with the netlist version which ships with sigrok. The same | |
1042 | * was observed with unused registers in the first page. | |
1043 | */ | |
1044 | return SR_ERR_NA; | |
1045 | ||
1046 | /* This is for research, currently does not work yet. */ | |
1047 | ret = sigma_check_open(sdi); | |
1048 | regaddr = 16; | |
1049 | regaddr = 14; | |
1050 | ret = sigma_set_register(devc, regaddr, 'F'); | |
1051 | ret = sigma_get_register(devc, regaddr, ®val); | |
1052 | sr_warn("%s() reg[%u] val[%u] rc[%d]", __func__, regaddr, regval, ret); | |
1053 | ret = sigma_check_close(devc); | |
1054 | return ret; | |
1055 | } | |
1056 | ||
1057 | /* Gets called after successful (volatile) hardware configuration. */ | |
1058 | SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi) | |
1059 | { | |
1060 | /* TODO See above, registers seem to not hold written data. */ | |
abcd4771 | 1061 | (void)sdi; |
53c8a99c | 1062 | return SR_ERR_NA; |
abcd4771 GS |
1063 | } |
1064 | ||
5e78a564 | 1065 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) |
f6564c8d | 1066 | { |
2c9c0df8 | 1067 | struct dev_context *devc; |
8e2d6c9d | 1068 | struct drv_context *drvc; |
5e78a564 | 1069 | uint64_t samplerate; |
2c9c0df8 | 1070 | int ret; |
3d9373af | 1071 | size_t num_channels; |
f6564c8d | 1072 | |
2c9c0df8 | 1073 | devc = sdi->priv; |
8e2d6c9d | 1074 | drvc = sdi->driver->context; |
f4abaa9f | 1075 | |
5e78a564 | 1076 | /* Accept any caller specified rate which the hardware supports. */ |
2d8a5089 | 1077 | ret = sigma_normalize_samplerate(devc->clock.samplerate, &samplerate); |
5e78a564 GS |
1078 | if (ret != SR_OK) |
1079 | return ret; | |
f6564c8d | 1080 | |
2f7e529c GS |
1081 | /* |
1082 | * Depending on the samplerates of 200/100/50- MHz, specific | |
1083 | * firmware is required and higher rates might limit the set | |
1084 | * of available channels. | |
1085 | */ | |
ac9534f4 | 1086 | num_channels = devc->num_channels; |
59df0c77 | 1087 | if (samplerate <= SR_MHZ(50)) { |
80e717b3 | 1088 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_50MHZ); |
ac9534f4 | 1089 | num_channels = 16; |
6b2d3385 | 1090 | } else if (samplerate == SR_MHZ(100)) { |
80e717b3 | 1091 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_100MHZ); |
ac9534f4 | 1092 | num_channels = 8; |
6b2d3385 | 1093 | } else if (samplerate == SR_MHZ(200)) { |
80e717b3 | 1094 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_200MHZ); |
ac9534f4 | 1095 | num_channels = 4; |
f78898e9 | 1096 | } |
f6564c8d | 1097 | |
2f7e529c | 1098 | /* |
5e78a564 GS |
1099 | * The samplerate affects the number of available logic channels |
1100 | * as well as a sample memory layout detail (the number of samples | |
1101 | * which the device will communicate within an "event"). | |
2f7e529c | 1102 | */ |
6b2d3385 | 1103 | if (ret == SR_OK) { |
ac9534f4 | 1104 | devc->num_channels = num_channels; |
6b2d3385 | 1105 | devc->samples_per_event = 16 / devc->num_channels; |
6b2d3385 | 1106 | } |
f6564c8d | 1107 | |
53c8a99c GS |
1108 | /* |
1109 | * Store the firmware type and most recently configured samplerate | |
1110 | * in hardware, such that subsequent sessions can start from there. | |
1111 | * This is a "best effort" approach. Failure is non-fatal. | |
1112 | */ | |
1113 | if (ret == SR_OK) | |
1114 | (void)sigma_store_hw_config(sdi); | |
1115 | ||
e8397563 | 1116 | return ret; |
28a35d8a HE |
1117 | } |
1118 | ||
98b43eb3 GS |
1119 | /* |
1120 | * Arrange for a session feed submit buffer. A queue where a number of | |
1121 | * samples gets accumulated to reduce the number of send calls. Which | |
1122 | * also enforces an optional sample count limit for data acquisition. | |
1123 | * | |
1124 | * The buffer holds up to CHUNK_SIZE bytes. The unit size is fixed (the | |
1125 | * driver provides a fixed channel layout regardless of samplerate). | |
1126 | */ | |
1127 | ||
1128 | #define CHUNK_SIZE (4 * 1024 * 1024) | |
1129 | ||
1130 | struct submit_buffer { | |
1131 | size_t unit_size; | |
1132 | size_t max_samples, curr_samples; | |
1133 | uint8_t *sample_data; | |
1134 | uint8_t *write_pointer; | |
1135 | struct sr_dev_inst *sdi; | |
1136 | struct sr_datafeed_packet packet; | |
1137 | struct sr_datafeed_logic logic; | |
98b43eb3 GS |
1138 | }; |
1139 | ||
1140 | static int alloc_submit_buffer(struct sr_dev_inst *sdi) | |
1141 | { | |
1142 | struct dev_context *devc; | |
1143 | struct submit_buffer *buffer; | |
1144 | size_t size; | |
1145 | ||
1146 | devc = sdi->priv; | |
1147 | ||
1148 | buffer = g_malloc0(sizeof(*buffer)); | |
1149 | devc->buffer = buffer; | |
1150 | ||
1151 | buffer->unit_size = sizeof(uint16_t); | |
1152 | size = CHUNK_SIZE; | |
1153 | size /= buffer->unit_size; | |
1154 | buffer->max_samples = size; | |
1155 | size *= buffer->unit_size; | |
1156 | buffer->sample_data = g_try_malloc0(size); | |
1157 | if (!buffer->sample_data) | |
1158 | return SR_ERR_MALLOC; | |
1159 | buffer->write_pointer = buffer->sample_data; | |
5e78a564 | 1160 | sr_sw_limits_init(&devc->feed_limits); |
98b43eb3 GS |
1161 | |
1162 | buffer->sdi = sdi; | |
1163 | memset(&buffer->logic, 0, sizeof(buffer->logic)); | |
1164 | buffer->logic.unitsize = buffer->unit_size; | |
1165 | buffer->logic.data = buffer->sample_data; | |
1166 | memset(&buffer->packet, 0, sizeof(buffer->packet)); | |
1167 | buffer->packet.type = SR_DF_LOGIC; | |
1168 | buffer->packet.payload = &buffer->logic; | |
1169 | ||
1170 | return SR_OK; | |
1171 | } | |
1172 | ||
5e78a564 | 1173 | static int setup_submit_limit(struct dev_context *devc) |
98b43eb3 | 1174 | { |
5e78a564 | 1175 | struct sr_sw_limits *limits; |
98b43eb3 GS |
1176 | int ret; |
1177 | GVariant *data; | |
1178 | uint64_t total; | |
1179 | ||
5e78a564 | 1180 | limits = &devc->feed_limits; |
98b43eb3 | 1181 | |
5e78a564 GS |
1182 | ret = sr_sw_limits_config_get(&devc->cfg_limits, |
1183 | SR_CONF_LIMIT_SAMPLES, &data); | |
1184 | if (ret != SR_OK) | |
1185 | return ret; | |
1186 | total = g_variant_get_uint64(data); | |
1187 | g_variant_unref(data); | |
1188 | ||
1189 | sr_sw_limits_init(limits); | |
98b43eb3 GS |
1190 | if (total) { |
1191 | data = g_variant_new_uint64(total); | |
5e78a564 | 1192 | ret = sr_sw_limits_config_set(limits, |
98b43eb3 GS |
1193 | SR_CONF_LIMIT_SAMPLES, data); |
1194 | g_variant_unref(data); | |
1195 | if (ret != SR_OK) | |
1196 | return ret; | |
1197 | } | |
1198 | ||
5e78a564 | 1199 | sr_sw_limits_acquisition_start(limits); |
98b43eb3 GS |
1200 | |
1201 | return SR_OK; | |
1202 | } | |
1203 | ||
1204 | static void free_submit_buffer(struct dev_context *devc) | |
1205 | { | |
1206 | struct submit_buffer *buffer; | |
1207 | ||
1208 | if (!devc) | |
1209 | return; | |
1210 | ||
1211 | buffer = devc->buffer; | |
1212 | if (!buffer) | |
1213 | return; | |
1214 | devc->buffer = NULL; | |
1215 | ||
1216 | g_free(buffer->sample_data); | |
1217 | g_free(buffer); | |
1218 | } | |
1219 | ||
1220 | static int flush_submit_buffer(struct dev_context *devc) | |
1221 | { | |
1222 | struct submit_buffer *buffer; | |
1223 | int ret; | |
1224 | ||
1225 | buffer = devc->buffer; | |
1226 | ||
1227 | /* Is queued sample data available? */ | |
1228 | if (!buffer->curr_samples) | |
1229 | return SR_OK; | |
1230 | ||
1231 | /* Submit to the session feed. */ | |
1232 | buffer->logic.length = buffer->curr_samples * buffer->unit_size; | |
1233 | ret = sr_session_send(buffer->sdi, &buffer->packet); | |
1234 | if (ret != SR_OK) | |
1235 | return ret; | |
1236 | ||
1237 | /* Rewind queue position. */ | |
1238 | buffer->curr_samples = 0; | |
1239 | buffer->write_pointer = buffer->sample_data; | |
1240 | ||
1241 | return SR_OK; | |
1242 | } | |
1243 | ||
1244 | static int addto_submit_buffer(struct dev_context *devc, | |
1245 | uint16_t sample, size_t count) | |
1246 | { | |
1247 | struct submit_buffer *buffer; | |
5e78a564 | 1248 | struct sr_sw_limits *limits; |
98b43eb3 GS |
1249 | int ret; |
1250 | ||
1251 | buffer = devc->buffer; | |
5e78a564 GS |
1252 | limits = &devc->feed_limits; |
1253 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
1254 | count = 0; |
1255 | ||
1256 | /* | |
1257 | * Individually accumulate and check each sample, such that | |
1258 | * accumulation between flushes won't exceed local storage, and | |
1259 | * enforcement of user specified limits is exact. | |
1260 | */ | |
1261 | while (count--) { | |
a53b8e4d | 1262 | write_u16le_inc(&buffer->write_pointer, sample); |
98b43eb3 GS |
1263 | buffer->curr_samples++; |
1264 | if (buffer->curr_samples == buffer->max_samples) { | |
1265 | ret = flush_submit_buffer(devc); | |
1266 | if (ret != SR_OK) | |
1267 | return ret; | |
1268 | } | |
5e78a564 GS |
1269 | sr_sw_limits_update_samples_read(limits, 1); |
1270 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
1271 | break; |
1272 | } | |
1273 | ||
1274 | return SR_OK; | |
1275 | } | |
1276 | ||
c53d793f HE |
1277 | /* |
1278 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
1279 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 1280 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
1281 | * |
1282 | * The Sigma supports complex triggers using boolean expressions, but this | |
1283 | * has not been implemented yet. | |
1284 | */ | |
3ba56876 | 1285 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 1286 | { |
39c64c6a BV |
1287 | struct dev_context *devc; |
1288 | struct sr_trigger *trigger; | |
1289 | struct sr_trigger_stage *stage; | |
1290 | struct sr_trigger_match *match; | |
1291 | const GSList *l, *m; | |
3d9373af GS |
1292 | uint16_t channelbit; |
1293 | size_t trigger_set; | |
57bbf56b | 1294 | |
39c64c6a | 1295 | devc = sdi->priv; |
5c231fc4 GS |
1296 | memset(&devc->trigger, 0, sizeof(devc->trigger)); |
1297 | trigger = sr_session_trigger_get(sdi->session); | |
1298 | if (!trigger) | |
39c64c6a BV |
1299 | return SR_OK; |
1300 | ||
1301 | trigger_set = 0; | |
1302 | for (l = trigger->stages; l; l = l->next) { | |
1303 | stage = l->data; | |
1304 | for (m = stage->matches; m; m = m->next) { | |
1305 | match = m->data; | |
9b4d261f | 1306 | /* Ignore disabled channels with a trigger. */ |
39c64c6a | 1307 | if (!match->channel->enabled) |
39c64c6a | 1308 | continue; |
a53b8e4d | 1309 | channelbit = 1 << match->channel->index; |
2d8a5089 | 1310 | if (devc->clock.samplerate >= SR_MHZ(100)) { |
39c64c6a BV |
1311 | /* Fast trigger support. */ |
1312 | if (trigger_set) { | |
88a5f9ea | 1313 | sr_err("100/200MHz modes limited to single trigger pin."); |
39c64c6a BV |
1314 | return SR_ERR; |
1315 | } | |
a53b8e4d | 1316 | if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 1317 | devc->trigger.fallingmask |= channelbit; |
a53b8e4d | 1318 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 1319 | devc->trigger.risingmask |= channelbit; |
a53b8e4d | 1320 | } else { |
88a5f9ea | 1321 | sr_err("100/200MHz modes limited to edge trigger."); |
39c64c6a BV |
1322 | return SR_ERR; |
1323 | } | |
eec5275e | 1324 | |
0a1f7b09 | 1325 | trigger_set++; |
39c64c6a BV |
1326 | } else { |
1327 | /* Simple trigger support (event). */ | |
1328 | if (match->match == SR_TRIGGER_ONE) { | |
1329 | devc->trigger.simplevalue |= channelbit; | |
1330 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 1331 | } else if (match->match == SR_TRIGGER_ZERO) { |
39c64c6a BV |
1332 | devc->trigger.simplevalue &= ~channelbit; |
1333 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 1334 | } else if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 1335 | devc->trigger.fallingmask |= channelbit; |
0a1f7b09 | 1336 | trigger_set++; |
8ebad343 | 1337 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 1338 | devc->trigger.risingmask |= channelbit; |
0a1f7b09 | 1339 | trigger_set++; |
39c64c6a BV |
1340 | } |
1341 | ||
1342 | /* | |
1343 | * Actually, Sigma supports 2 rising/falling triggers, | |
1344 | * but they are ORed and the current trigger syntax | |
1345 | * does not permit ORed triggers. | |
1346 | */ | |
1347 | if (trigger_set > 1) { | |
88a5f9ea | 1348 | sr_err("Limited to 1 edge trigger."); |
39c64c6a BV |
1349 | return SR_ERR; |
1350 | } | |
ee492173 | 1351 | } |
ee492173 | 1352 | } |
57bbf56b HE |
1353 | } |
1354 | ||
e46b8fb1 | 1355 | return SR_OK; |
57bbf56b HE |
1356 | } |
1357 | ||
36b1c8e6 | 1358 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 1359 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
9b4d261f | 1360 | struct sigma_trigger *t) |
36b1c8e6 | 1361 | { |
a53b8e4d | 1362 | const uint8_t *rdptr; |
3d9373af | 1363 | size_t i; |
a53b8e4d | 1364 | uint16_t sample; |
36b1c8e6 | 1365 | |
a53b8e4d GS |
1366 | rdptr = samples; |
1367 | sample = 0; | |
0a1f7b09 | 1368 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 1369 | if (i > 0) |
5fc01191 | 1370 | last_sample = sample; |
a53b8e4d | 1371 | sample = read_u16le_inc(&rdptr); |
36b1c8e6 HE |
1372 | |
1373 | /* Simple triggers. */ | |
5fc01191 | 1374 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
1375 | continue; |
1376 | ||
1377 | /* Rising edge. */ | |
5fc01191 MV |
1378 | if (((last_sample & t->risingmask) != 0) || |
1379 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
1380 | continue; |
1381 | ||
1382 | /* Falling edge. */ | |
bdfc7a89 | 1383 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 1384 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
1385 | continue; |
1386 | ||
1387 | break; | |
1388 | } | |
1389 | ||
1390 | /* If we did not match, return original trigger pos. */ | |
1391 | return i & 0x7; | |
1392 | } | |
1393 | ||
98b43eb3 GS |
1394 | static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample) |
1395 | { | |
1396 | /* TODO | |
1397 | * Check whether the combination of this very sample and the | |
1398 | * previous state match the configured trigger condition. This | |
1399 | * improves the resolution of the trigger marker's position. | |
1400 | * The hardware provided position is coarse, and may point to | |
1401 | * a position before the actual match. | |
1402 | * | |
1403 | * See the previous get_trigger_offset() implementation. This | |
1404 | * code needs to get re-used here. | |
1405 | */ | |
1406 | (void)devc; | |
1407 | (void)sample; | |
1408 | (void)get_trigger_offset; | |
1409 | ||
1410 | return FALSE; | |
1411 | } | |
1412 | ||
1413 | static int check_and_submit_sample(struct dev_context *devc, | |
1414 | uint16_t sample, size_t count, gboolean check_trigger) | |
1415 | { | |
1416 | gboolean triggered; | |
1417 | int ret; | |
1418 | ||
1419 | triggered = check_trigger && sample_matches_trigger(devc, sample); | |
1420 | if (triggered) { | |
1421 | ret = flush_submit_buffer(devc); | |
1422 | if (ret != SR_OK) | |
1423 | return ret; | |
1424 | ret = std_session_send_df_trigger(devc->buffer->sdi); | |
1425 | if (ret != SR_OK) | |
1426 | return ret; | |
1427 | } | |
1428 | ||
1429 | ret = addto_submit_buffer(devc, sample, count); | |
1430 | if (ret != SR_OK) | |
1431 | return ret; | |
1432 | ||
1433 | return SR_OK; | |
1434 | } | |
1435 | ||
3513d965 MV |
1436 | /* |
1437 | * Return the timestamp of "DRAM cluster". | |
1438 | */ | |
1439 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
1440 | { | |
2a62a9c4 | 1441 | return read_u16le((const uint8_t *)&cluster->timestamp); |
3513d965 MV |
1442 | } |
1443 | ||
0498f743 GS |
1444 | /* |
1445 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
1446 | */ | |
1447 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
1448 | { | |
2a62a9c4 | 1449 | return read_u16le((const uint8_t *)&cl->samples[idx]); |
0498f743 GS |
1450 | } |
1451 | ||
85c032e4 GS |
1452 | /* |
1453 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
1454 | * One 16bit item contains two samples of 8bits each. The bits of | |
1455 | * multiple samples are interleaved. | |
1456 | */ | |
1457 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
1458 | { | |
1459 | uint16_t outdata; | |
1460 | ||
1461 | indata >>= idx; | |
1462 | outdata = 0; | |
1463 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
1464 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
1465 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
1466 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
1467 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
1468 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
1469 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
1470 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
1471 | return outdata; | |
1472 | } | |
1473 | ||
1474 | /* | |
1475 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
1476 | * One 16bit item contains four samples of 4bits each. The bits of | |
1477 | * multiple samples are interleaved. | |
1478 | */ | |
1479 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
1480 | { | |
1481 | uint16_t outdata; | |
1482 | ||
1483 | indata >>= idx; | |
1484 | outdata = 0; | |
1485 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
1486 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
1487 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
1488 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
1489 | return outdata; | |
1490 | } | |
1491 | ||
98b43eb3 GS |
1492 | static void sigma_decode_dram_cluster(struct dev_context *devc, |
1493 | struct sigma_dram_cluster *dram_cluster, | |
1494 | size_t events_in_cluster, gboolean triggered) | |
23239b5c | 1495 | { |
98b43eb3 | 1496 | struct sigma_state *ss; |
85c032e4 | 1497 | uint16_t tsdiff, ts, sample, item16; |
3d9373af GS |
1498 | size_t count; |
1499 | size_t evt; | |
23239b5c | 1500 | |
98b43eb3 GS |
1501 | if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER) |
1502 | triggered = FALSE; | |
23239b5c MV |
1503 | |
1504 | /* | |
468f17f2 GS |
1505 | * If this cluster is not adjacent to the previously received |
1506 | * cluster, then send the appropriate number of samples with the | |
1507 | * previous values to the sigrok session. This "decodes RLE". | |
2c33b092 | 1508 | * |
98b43eb3 GS |
1509 | * These samples cannot match the trigger since they just repeat |
1510 | * the previously submitted data pattern. (This assumption holds | |
1511 | * for simple level and edge triggers. It would not for timed or | |
1512 | * counted conditions, which currently are not supported.) | |
23239b5c | 1513 | */ |
98b43eb3 GS |
1514 | ss = &devc->state; |
1515 | ts = sigma_dram_cluster_ts(dram_cluster); | |
1516 | tsdiff = ts - ss->lastts; | |
1517 | if (tsdiff > 0) { | |
9b4d261f | 1518 | sample = ss->lastsample; |
98b43eb3 | 1519 | count = tsdiff * devc->samples_per_event; |
9b4d261f | 1520 | (void)check_and_submit_sample(devc, sample, count, FALSE); |
23239b5c | 1521 | } |
98b43eb3 | 1522 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
1523 | |
1524 | /* | |
98b43eb3 GS |
1525 | * Grab sample data from the current cluster and prepare their |
1526 | * submission to the session feed. Handle samplerate dependent | |
1527 | * memory layout of sample data. Accumulation of data chunks | |
1528 | * before submission is transparent to this code path, specific | |
1529 | * buffer depth is neither assumed nor required here. | |
23239b5c | 1530 | */ |
0498f743 | 1531 | sample = 0; |
3d9373af GS |
1532 | for (evt = 0; evt < events_in_cluster; evt++) { |
1533 | item16 = sigma_dram_cluster_data(dram_cluster, evt); | |
2d8a5089 | 1534 | if (devc->clock.samplerate == SR_MHZ(200)) { |
85c032e4 | 1535 | sample = sigma_deinterlace_200mhz_data(item16, 0); |
98b43eb3 | 1536 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1537 | sample = sigma_deinterlace_200mhz_data(item16, 1); |
98b43eb3 | 1538 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1539 | sample = sigma_deinterlace_200mhz_data(item16, 2); |
98b43eb3 | 1540 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1541 | sample = sigma_deinterlace_200mhz_data(item16, 3); |
98b43eb3 | 1542 | check_and_submit_sample(devc, sample, 1, triggered); |
2d8a5089 | 1543 | } else if (devc->clock.samplerate == SR_MHZ(100)) { |
85c032e4 | 1544 | sample = sigma_deinterlace_100mhz_data(item16, 0); |
98b43eb3 | 1545 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1546 | sample = sigma_deinterlace_100mhz_data(item16, 1); |
98b43eb3 | 1547 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 GS |
1548 | } else { |
1549 | sample = item16; | |
98b43eb3 | 1550 | check_and_submit_sample(devc, sample, 1, triggered); |
23239b5c | 1551 | } |
23239b5c | 1552 | } |
0498f743 | 1553 | ss->lastsample = sample; |
23239b5c MV |
1554 | } |
1555 | ||
28a35d8a | 1556 | /* |
fefa1800 UH |
1557 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
1558 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
1559 | * |
1560 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
1561 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
1562 | * For 50 MHz and below, events contain one sample for each channel, | |
1563 | * spread 20 ns apart. | |
28a35d8a | 1564 | */ |
98b43eb3 GS |
1565 | static int decode_chunk_ts(struct dev_context *devc, |
1566 | struct sigma_dram_line *dram_line, | |
1567 | size_t events_in_line, size_t trigger_event) | |
28a35d8a | 1568 | { |
3628074d | 1569 | struct sigma_dram_cluster *dram_cluster; |
3d9373af GS |
1570 | size_t clusters_in_line; |
1571 | size_t events_in_cluster; | |
1572 | size_t cluster; | |
1573 | size_t trigger_cluster; | |
f06fb3e9 | 1574 | |
f06fb3e9 GS |
1575 | clusters_in_line = events_in_line; |
1576 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
1577 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
ee492173 | 1578 | |
4ae1f451 | 1579 | /* Check if trigger is in this chunk. */ |
3d9373af | 1580 | trigger_cluster = ~0UL; |
2c33b092 | 1581 | if (trigger_event < EVENTS_PER_ROW) { |
2d8a5089 | 1582 | if (devc->clock.samplerate <= SR_MHZ(50)) { |
1e23158b MV |
1583 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, |
1584 | trigger_event); | |
1585 | } | |
57bbf56b | 1586 | |
f3f19d11 | 1587 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 1588 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1589 | } |
28a35d8a | 1590 | |
5fc01191 | 1591 | /* For each full DRAM cluster. */ |
3d9373af GS |
1592 | for (cluster = 0; cluster < clusters_in_line; cluster++) { |
1593 | dram_cluster = &dram_line->cluster[cluster]; | |
5fc01191 | 1594 | |
5fc01191 | 1595 | /* The last cluster might not be full. */ |
3d9373af | 1596 | if ((cluster == clusters_in_line - 1) && |
23239b5c | 1597 | (events_in_line % EVENTS_PER_CLUSTER)) { |
5fc01191 | 1598 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1599 | } else { |
5fc01191 | 1600 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1601 | } |
ee492173 | 1602 | |
98b43eb3 | 1603 | sigma_decode_dram_cluster(devc, dram_cluster, |
3d9373af | 1604 | events_in_cluster, cluster == trigger_cluster); |
28a35d8a HE |
1605 | } |
1606 | ||
e46b8fb1 | 1607 | return SR_OK; |
28a35d8a HE |
1608 | } |
1609 | ||
6057d9fa | 1610 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1611 | { |
e15e5873 | 1612 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
1613 | |
1614 | struct dev_context *devc; | |
fd830beb | 1615 | struct sigma_dram_line *dram_line; |
462fe786 | 1616 | uint32_t stoppos, triggerpos; |
6057d9fa | 1617 | uint8_t modestatus; |
3d9373af GS |
1618 | size_t line_idx; |
1619 | size_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
1620 | size_t dl_first_line, dl_line; | |
1621 | size_t dl_events_in_line, trigger_event; | |
1622 | size_t trg_line, trg_event; | |
98b43eb3 | 1623 | int ret; |
f06fb3e9 GS |
1624 | |
1625 | devc = sdi->priv; | |
c6648b66 | 1626 | |
6868626b | 1627 | sr_info("Downloading sample data."); |
dde0175d | 1628 | devc->state.state = SIGMA_DOWNLOAD; |
6868626b | 1629 | |
22f64ed8 GS |
1630 | /* |
1631 | * Ask the hardware to stop data acquisition. Reception of the | |
1632 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1633 | * clusters to DRAM regardless of whether pin state changes) and | |
1634 | * raise the POSTTRIGGERED flag. | |
1635 | */ | |
88a5f9ea GS |
1636 | modestatus = WMR_FORCESTOP | WMR_SDRAMWRITEEN; |
1637 | ret = sigma_set_register(devc, WRITE_MODE, modestatus); | |
1638 | if (ret != SR_OK) | |
1639 | return ret; | |
22f64ed8 | 1640 | do { |
0f017b7d | 1641 | ret = sigma_get_register(devc, READ_MODE, &modestatus); |
88a5f9ea GS |
1642 | if (ret != SR_OK) { |
1643 | sr_err("Could not poll for post-trigger state."); | |
f73b00b6 DT |
1644 | return FALSE; |
1645 | } | |
22f64ed8 | 1646 | } while (!(modestatus & RMR_POSTTRIGGERED)); |
6057d9fa MV |
1647 | |
1648 | /* Set SDRAM Read Enable. */ | |
88a5f9ea GS |
1649 | ret = sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN); |
1650 | if (ret != SR_OK) | |
1651 | return ret; | |
6057d9fa | 1652 | |
88a5f9ea GS |
1653 | /* Get the current position. Check if trigger has fired. */ |
1654 | ret = sigma_read_pos(devc, &stoppos, &triggerpos, &modestatus); | |
1655 | if (ret != SR_OK) { | |
1656 | sr_err("Could not query capture positions/state."); | |
f73b00b6 DT |
1657 | return FALSE; |
1658 | } | |
3d9373af GS |
1659 | trg_line = ~0UL; |
1660 | trg_event = ~0UL; | |
22f64ed8 | 1661 | if (modestatus & RMR_TRIGGERED) { |
a53b8e4d GS |
1662 | trg_line = triggerpos >> ROW_SHIFT; |
1663 | trg_event = triggerpos & ROW_MASK; | |
1e23158b | 1664 | } |
6057d9fa | 1665 | |
c6648b66 | 1666 | /* |
74d453ab GS |
1667 | * Determine how many "DRAM lines" of 1024 bytes each we need to |
1668 | * retrieve from the Sigma hardware, so that we have a complete | |
1669 | * set of samples. Note that the last line need not contain 64 | |
1670 | * clusters, it might be partially filled only. | |
1671 | * | |
1672 | * When RMR_ROUND is set, the circular buffer in DRAM has wrapped | |
1673 | * around. Since the status of the very next line is uncertain in | |
2c33b092 | 1674 | * that case, we skip it and start reading from the next line. |
c6648b66 | 1675 | */ |
2c33b092 GS |
1676 | dl_first_line = 0; |
1677 | dl_lines_total = (stoppos >> ROW_SHIFT) + 1; | |
74d453ab GS |
1678 | if (modestatus & RMR_ROUND) { |
1679 | dl_first_line = dl_lines_total + 1; | |
2c33b092 | 1680 | dl_lines_total = ROW_COUNT - 2; |
74d453ab | 1681 | } |
44081095 DT |
1682 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1683 | if (!dram_line) | |
1684 | return FALSE; | |
98b43eb3 GS |
1685 | ret = alloc_submit_buffer(sdi); |
1686 | if (ret != SR_OK) | |
1687 | return FALSE; | |
5e78a564 | 1688 | ret = setup_submit_limit(devc); |
98b43eb3 GS |
1689 | if (ret != SR_OK) |
1690 | return FALSE; | |
c6648b66 | 1691 | dl_lines_done = 0; |
c6648b66 MV |
1692 | while (dl_lines_total > dl_lines_done) { |
1693 | /* We can download only up-to 32 DRAM lines in one go! */ | |
547c4cdc | 1694 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); |
6868626b | 1695 | |
74d453ab | 1696 | dl_line = dl_first_line + dl_lines_done; |
2c33b092 | 1697 | dl_line %= ROW_COUNT; |
88a5f9ea GS |
1698 | ret = sigma_read_dram(devc, dl_line, dl_lines_curr, |
1699 | (uint8_t *)dram_line); | |
1700 | if (ret != SR_OK) | |
1701 | return FALSE; | |
6868626b | 1702 | |
c6648b66 MV |
1703 | /* This is the first DRAM line, so find the initial timestamp. */ |
1704 | if (dl_lines_done == 0) { | |
3513d965 MV |
1705 | devc->state.lastts = |
1706 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1707 | devc->state.lastsample = 0; |
6868626b BV |
1708 | } |
1709 | ||
3d9373af | 1710 | for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) { |
a53b8e4d | 1711 | /* The last "DRAM line" need not span its full length. */ |
5c231fc4 | 1712 | dl_events_in_line = EVENTS_PER_ROW; |
3d9373af | 1713 | if (dl_lines_done + line_idx == dl_lines_total - 1) |
a53b8e4d | 1714 | dl_events_in_line = stoppos & ROW_MASK; |
c6648b66 | 1715 | |
e69ad48e | 1716 | /* Test if the trigger happened on this line. */ |
3d9373af GS |
1717 | trigger_event = ~0UL; |
1718 | if (dl_lines_done + line_idx == trg_line) | |
1e23158b | 1719 | trigger_event = trg_event; |
e69ad48e | 1720 | |
3d9373af | 1721 | decode_chunk_ts(devc, dram_line + line_idx, |
98b43eb3 | 1722 | dl_events_in_line, trigger_event); |
c6648b66 | 1723 | } |
6868626b | 1724 | |
c6648b66 | 1725 | dl_lines_done += dl_lines_curr; |
6868626b | 1726 | } |
98b43eb3 GS |
1727 | flush_submit_buffer(devc); |
1728 | free_submit_buffer(devc); | |
dde0175d | 1729 | g_free(dram_line); |
6868626b | 1730 | |
bee2b016 | 1731 | std_session_send_df_end(sdi); |
6057d9fa | 1732 | |
dde0175d | 1733 | devc->state.state = SIGMA_IDLE; |
d2f7c417 | 1734 | sr_dev_acquisition_stop(sdi); |
6057d9fa MV |
1735 | |
1736 | return TRUE; | |
6868626b BV |
1737 | } |
1738 | ||
d4051930 | 1739 | /* |
74d453ab GS |
1740 | * Periodically check the Sigma status when in CAPTURE mode. This routine |
1741 | * checks whether the configured sample count or sample time have passed, | |
1742 | * and will stop acquisition and download the acquired samples. | |
d4051930 MV |
1743 | */ |
1744 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1745 | { |
f06fb3e9 | 1746 | struct dev_context *devc; |
28a35d8a | 1747 | |
f06fb3e9 | 1748 | devc = sdi->priv; |
5e78a564 | 1749 | if (sr_sw_limits_check(&devc->acq_limits)) |
6057d9fa | 1750 | return download_capture(sdi); |
00c86508 | 1751 | |
d4051930 MV |
1752 | return TRUE; |
1753 | } | |
28a35d8a | 1754 | |
3ba56876 | 1755 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1756 | { |
1757 | struct sr_dev_inst *sdi; | |
1758 | struct dev_context *devc; | |
88c51afe | 1759 | |
d4051930 MV |
1760 | (void)fd; |
1761 | (void)revents; | |
88c51afe | 1762 | |
d4051930 MV |
1763 | sdi = cb_data; |
1764 | devc = sdi->priv; | |
1765 | ||
1766 | if (devc->state.state == SIGMA_IDLE) | |
1767 | return TRUE; | |
1768 | ||
dde0175d GS |
1769 | /* |
1770 | * When the application has requested to stop the acquisition, | |
1771 | * then immediately start downloading sample data. Otherwise | |
1772 | * keep checking configured limits which will terminate the | |
1773 | * acquisition and initiate download. | |
1774 | */ | |
1775 | if (devc->state.state == SIGMA_STOPPING) | |
1776 | return download_capture(sdi); | |
d4051930 MV |
1777 | if (devc->state.state == SIGMA_CAPTURE) |
1778 | return sigma_capture_mode(sdi); | |
28a35d8a | 1779 | |
28a35d8a HE |
1780 | return TRUE; |
1781 | } | |
1782 | ||
c53d793f | 1783 | /* Build a LUT entry used by the trigger functions. */ |
7dd766e0 GS |
1784 | static void build_lut_entry(uint16_t *lut_entry, |
1785 | uint16_t spec_value, uint16_t spec_mask) | |
ee492173 | 1786 | { |
7dd766e0 GS |
1787 | size_t quad, bitidx, ch; |
1788 | uint16_t quadmask, bitmask; | |
1789 | gboolean spec_value_low, bit_idx_low; | |
ee492173 | 1790 | |
7dd766e0 GS |
1791 | /* |
1792 | * For each quad-channel-group, for each bit in the LUT (each | |
1793 | * bit pattern of the channel signals, aka LUT address), for | |
1794 | * each channel in the quad, setup the bit in the LUT entry. | |
1795 | * | |
1796 | * Start from all-ones in the LUT (true, always matches), then | |
1797 | * "pessimize the truthness" for specified conditions. | |
1798 | */ | |
1799 | for (quad = 0; quad < 4; quad++) { | |
1800 | lut_entry[quad] = ~0; | |
1801 | for (bitidx = 0; bitidx < 16; bitidx++) { | |
1802 | for (ch = 0; ch < 4; ch++) { | |
1803 | quadmask = 1 << ch; | |
1804 | bitmask = quadmask << (quad * 4); | |
1805 | if (!(spec_mask & bitmask)) | |
1806 | continue; | |
1807 | /* | |
1808 | * This bit is part of the spec. The | |
1809 | * condition which gets checked here | |
1810 | * (got checked in all implementations | |
1811 | * so far) is uncertain. A bit position | |
1812 | * in the current index' number(!) is | |
1813 | * checked? | |
1814 | */ | |
1815 | spec_value_low = !(spec_value & bitmask); | |
1816 | bit_idx_low = !(bitidx & quadmask); | |
1817 | if (spec_value_low == bit_idx_low) | |
1818 | continue; | |
1819 | lut_entry[quad] &= ~(1 << bitidx); | |
ee492173 | 1820 | } |
a53b8e4d | 1821 | } |
ee492173 | 1822 | } |
c53d793f | 1823 | } |
ee492173 | 1824 | |
c53d793f HE |
1825 | /* Add a logical function to LUT mask. */ |
1826 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
3d9373af | 1827 | size_t index, gboolean neg, uint16_t *mask) |
c53d793f | 1828 | { |
3d9373af | 1829 | size_t i, j; |
c53d793f HE |
1830 | int x[2][2], tmp, a, b, aset, bset, rset; |
1831 | ||
5c231fc4 | 1832 | memset(x, 0, sizeof(x)); |
c53d793f HE |
1833 | |
1834 | /* Trigger detect condition. */ | |
1835 | switch (oper) { | |
1836 | case OP_LEVEL: | |
1837 | x[0][1] = 1; | |
1838 | x[1][1] = 1; | |
1839 | break; | |
1840 | case OP_NOT: | |
1841 | x[0][0] = 1; | |
1842 | x[1][0] = 1; | |
1843 | break; | |
1844 | case OP_RISE: | |
1845 | x[0][1] = 1; | |
1846 | break; | |
1847 | case OP_FALL: | |
1848 | x[1][0] = 1; | |
1849 | break; | |
1850 | case OP_RISEFALL: | |
1851 | x[0][1] = 1; | |
1852 | x[1][0] = 1; | |
1853 | break; | |
1854 | case OP_NOTRISE: | |
1855 | x[1][1] = 1; | |
1856 | x[0][0] = 1; | |
1857 | x[1][0] = 1; | |
1858 | break; | |
1859 | case OP_NOTFALL: | |
1860 | x[1][1] = 1; | |
1861 | x[0][0] = 1; | |
1862 | x[0][1] = 1; | |
1863 | break; | |
1864 | case OP_NOTRISEFALL: | |
1865 | x[1][1] = 1; | |
1866 | x[0][0] = 1; | |
1867 | break; | |
1868 | } | |
1869 | ||
1870 | /* Transpose if neg is set. */ | |
1871 | if (neg) { | |
0a1f7b09 UH |
1872 | for (i = 0; i < 2; i++) { |
1873 | for (j = 0; j < 2; j++) { | |
c53d793f | 1874 | tmp = x[i][j]; |
0a1f7b09 UH |
1875 | x[i][j] = x[1 - i][1 - j]; |
1876 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1877 | } |
ea9cfed7 | 1878 | } |
c53d793f HE |
1879 | } |
1880 | ||
1881 | /* Update mask with function. */ | |
0a1f7b09 | 1882 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1883 | a = (i >> (2 * index + 0)) & 1; |
1884 | b = (i >> (2 * index + 1)) & 1; | |
1885 | ||
1886 | aset = (*mask >> i) & 1; | |
1887 | bset = x[b][a]; | |
1888 | ||
382cb19f | 1889 | rset = 0; |
c53d793f HE |
1890 | if (func == FUNC_AND || func == FUNC_NAND) |
1891 | rset = aset & bset; | |
1892 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1893 | rset = aset | bset; | |
1894 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1895 | rset = aset ^ bset; | |
1896 | ||
1897 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1898 | rset = !rset; | |
1899 | ||
1900 | *mask &= ~(1 << i); | |
1901 | ||
1902 | if (rset) | |
1903 | *mask |= 1 << i; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | /* | |
1908 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1909 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1910 | * set at any time, but a full mask and value can be set (0/1). | |
1911 | */ | |
9b4d261f GS |
1912 | SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, |
1913 | struct triggerlut *lut) | |
c53d793f | 1914 | { |
5c231fc4 | 1915 | uint16_t masks[2]; |
3d9373af | 1916 | size_t bitidx, condidx; |
7dd766e0 | 1917 | uint16_t value, mask; |
c53d793f | 1918 | |
7dd766e0 | 1919 | /* Start assuming simple triggers. */ |
5c231fc4 | 1920 | memset(lut, 0, sizeof(*lut)); |
c53d793f | 1921 | lut->m4 = 0xa000; |
16791da9 | 1922 | lut->m3q = 0xffff; |
c53d793f | 1923 | |
7dd766e0 GS |
1924 | /* Process value/mask triggers. */ |
1925 | value = devc->trigger.simplevalue; | |
1926 | mask = devc->trigger.simplemask; | |
1927 | build_lut_entry(lut->m2d, value, mask); | |
c53d793f | 1928 | |
7dd766e0 GS |
1929 | /* Scan for and process rise/fall triggers. */ |
1930 | memset(&masks, 0, sizeof(masks)); | |
1931 | condidx = 0; | |
1932 | for (bitidx = 0; bitidx < 16; bitidx++) { | |
1933 | mask = 1 << bitidx; | |
1934 | value = devc->trigger.risingmask | devc->trigger.fallingmask; | |
1935 | if (!(value & mask)) | |
1936 | continue; | |
1937 | if (condidx == 0) | |
1938 | build_lut_entry(lut->m0d, mask, mask); | |
1939 | if (condidx == 1) | |
1940 | build_lut_entry(lut->m1d, mask, mask); | |
1941 | masks[condidx++] = mask; | |
1942 | if (condidx == ARRAY_SIZE(masks)) | |
1943 | break; | |
c53d793f HE |
1944 | } |
1945 | ||
7dd766e0 | 1946 | /* Add glue logic for rise/fall triggers. */ |
c53d793f | 1947 | if (masks[0] || masks[1]) { |
16791da9 | 1948 | lut->m3q = 0; |
0e1357e8 | 1949 | if (masks[0] & devc->trigger.risingmask) |
16791da9 | 1950 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3q); |
0e1357e8 | 1951 | if (masks[0] & devc->trigger.fallingmask) |
16791da9 | 1952 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3q); |
0e1357e8 | 1953 | if (masks[1] & devc->trigger.risingmask) |
16791da9 | 1954 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3q); |
0e1357e8 | 1955 | if (masks[1] & devc->trigger.fallingmask) |
16791da9 | 1956 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3q); |
c53d793f | 1957 | } |
ee492173 | 1958 | |
c53d793f | 1959 | /* Triggertype: event. */ |
16791da9 GS |
1960 | lut->params.selres = TRGSEL_SELCODE_NEVER; |
1961 | lut->params.selinc = TRGSEL_SELCODE_LEVEL; | |
1962 | lut->params.sela = 0; /* Counter >= CMPA && LEVEL */ | |
1963 | lut->params.cmpa = 0; /* Count 0 -> 1 already triggers. */ | |
ee492173 | 1964 | |
e46b8fb1 | 1965 | return SR_OK; |
ee492173 | 1966 | } |