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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
28a35d8a HE |
30 | #include "asix-sigma.h" |
31 | ||
32 | #define USB_VENDOR 0xa600 | |
33 | #define USB_PRODUCT 0xa000 | |
34 | #define USB_DESCRIPTION "ASIX SIGMA" | |
35 | #define USB_VENDOR_NAME "ASIX" | |
36 | #define USB_MODEL_NAME "SIGMA" | |
37 | #define USB_MODEL_VERSION "" | |
57bbf56b | 38 | #define TRIGGER_TYPES "rf" |
28a35d8a HE |
39 | |
40 | static GSList *device_instances = NULL; | |
41 | ||
42 | // XXX These should be per device | |
43 | static struct ftdi_context ftdic; | |
f78898e9 | 44 | static uint64_t cur_samplerate = 0; |
28a35d8a HE |
45 | static uint32_t limit_msec = 0; |
46 | static struct timeval start_tv; | |
f6564c8d | 47 | static int cur_firmware = -1; |
f78898e9 HE |
48 | static int num_probes = 0; |
49 | static int samples_per_event = 0; | |
57bbf56b HE |
50 | static int capture_ratio = 50; |
51 | ||
52 | /* Single-pin trigger support */ | |
53 | static uint8_t triggerpin = 1; | |
54 | static uint8_t triggerfall = 0; | |
28a35d8a HE |
55 | |
56 | static uint64_t supported_samplerates[] = { | |
ed09fd07 | 57 | KHZ(200), |
edca2c5c | 58 | KHZ(250), |
ed09fd07 | 59 | KHZ(500), |
edca2c5c | 60 | MHZ(1), |
ed09fd07 | 61 | MHZ(5), |
edca2c5c HE |
62 | MHZ(10), |
63 | MHZ(25), | |
e8397563 HE |
64 | MHZ(50), |
65 | MHZ(100), | |
28a35d8a HE |
66 | MHZ(200), |
67 | 0, | |
68 | }; | |
69 | ||
70 | static struct samplerates samplerates = { | |
ed09fd07 | 71 | KHZ(200), |
28a35d8a HE |
72 | MHZ(200), |
73 | 0, | |
74 | supported_samplerates, | |
75 | }; | |
76 | ||
77 | static int capabilities[] = { | |
78 | HWCAP_LOGIC_ANALYZER, | |
79 | HWCAP_SAMPLERATE, | |
57bbf56b HE |
80 | HWCAP_CAPTURE_RATIO, |
81 | HWCAP_PROBECONFIG, | |
28a35d8a HE |
82 | |
83 | /* These are really implemented in the driver, not the hardware. */ | |
84 | HWCAP_LIMIT_MSEC, | |
85 | 0, | |
86 | }; | |
87 | ||
fefa1800 UH |
88 | /* Force the FPGA to reboot. */ |
89 | static uint8_t suicide[] = { | |
90 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
91 | }; | |
92 | ||
93 | /* Prepare to upload firmware (FPGA specific). */ | |
94 | static uint8_t init[] = { | |
95 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
96 | }; | |
97 | ||
98 | /* Initialize the logic analyzer mode. */ | |
99 | static uint8_t logic_mode_start[] = { | |
100 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
101 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
102 | }; | |
103 | ||
f6564c8d HE |
104 | static const char *firmware_files[] = |
105 | { | |
a8116d76 HE |
106 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
107 | "asix-sigma-100.fw", /* 100 MHz */ | |
108 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 109 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 110 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
111 | }; |
112 | ||
9ddb2a12 | 113 | static int sigma_read(void *buf, size_t size) |
28a35d8a HE |
114 | { |
115 | int ret; | |
fefa1800 UH |
116 | |
117 | ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
118 | if (ret < 0) { |
119 | g_warning("ftdi_read_data failed: %s", | |
fefa1800 | 120 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
121 | } |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
fefa1800 | 126 | static int sigma_write(void *buf, size_t size) |
28a35d8a HE |
127 | { |
128 | int ret; | |
fefa1800 UH |
129 | |
130 | ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
131 | if (ret < 0) { |
132 | g_warning("ftdi_write_data failed: %s", | |
fefa1800 UH |
133 | ftdi_get_error_string(&ftdic)); |
134 | } else if ((size_t) ret != size) { | |
28a35d8a HE |
135 | g_warning("ftdi_write_data did not complete write\n"); |
136 | } | |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
141 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len) | |
142 | { | |
143 | size_t i; | |
144 | uint8_t buf[len + 2]; | |
145 | int idx = 0; | |
146 | ||
147 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
148 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
149 | ||
fefa1800 | 150 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
151 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
152 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
153 | } | |
154 | ||
155 | return sigma_write(buf, idx); | |
156 | } | |
157 | ||
158 | static int sigma_set_register(uint8_t reg, uint8_t value) | |
159 | { | |
160 | return sigma_write_register(reg, &value, 1); | |
161 | } | |
162 | ||
163 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len) | |
164 | { | |
165 | uint8_t buf[3]; | |
fefa1800 | 166 | |
28a35d8a HE |
167 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
168 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
169 | buf[2] = REG_READ_ADDR; |
170 | ||
171 | sigma_write(buf, sizeof(buf)); | |
172 | ||
173 | return sigma_read(data, len); | |
174 | } | |
175 | ||
176 | static uint8_t sigma_get_register(uint8_t reg) | |
177 | { | |
178 | uint8_t value; | |
fefa1800 | 179 | |
28a35d8a HE |
180 | if (1 != sigma_read_register(reg, &value, 1)) { |
181 | g_warning("Sigma_get_register: 1 byte expected"); | |
182 | return 0; | |
183 | } | |
184 | ||
185 | return value; | |
186 | } | |
187 | ||
188 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos) | |
189 | { | |
190 | uint8_t buf[] = { | |
191 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
192 | ||
193 | REG_READ_ADDR | NEXT_REG, | |
194 | REG_READ_ADDR | NEXT_REG, | |
195 | REG_READ_ADDR | NEXT_REG, | |
196 | REG_READ_ADDR | NEXT_REG, | |
197 | REG_READ_ADDR | NEXT_REG, | |
198 | REG_READ_ADDR | NEXT_REG, | |
199 | }; | |
28a35d8a HE |
200 | uint8_t result[6]; |
201 | ||
202 | sigma_write(buf, sizeof(buf)); | |
203 | ||
204 | sigma_read(result, sizeof(result)); | |
205 | ||
206 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
207 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
208 | ||
57bbf56b HE |
209 | /* Not really sure why this must be done, but according to spec. */ |
210 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
211 | stoppos -= 64; | |
212 | ||
213 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
214 | triggerpos -= 64; | |
215 | ||
28a35d8a HE |
216 | return 1; |
217 | } | |
218 | ||
219 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data) | |
220 | { | |
221 | size_t i; | |
222 | uint8_t buf[4096]; | |
223 | int idx = 0; | |
224 | ||
fefa1800 | 225 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
226 | buf[0] = startchunk >> 8; |
227 | buf[1] = startchunk & 0xff; | |
228 | sigma_write_register(WRITE_MEMROW, buf, 2); | |
229 | ||
fefa1800 | 230 | /* Read the DRAM. */ |
28a35d8a HE |
231 | buf[idx++] = REG_DRAM_BLOCK; |
232 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
233 | ||
234 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
235 | /* Alternate bit to copy from DRAM to cache. */ |
236 | if (i != (numchunks - 1)) | |
237 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
238 | |
239 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
240 | ||
fefa1800 | 241 | if (i != (numchunks - 1)) |
28a35d8a HE |
242 | buf[idx++] = REG_DRAM_WAIT_ACK; |
243 | } | |
244 | ||
245 | sigma_write(buf, idx); | |
246 | ||
247 | return sigma_read(data, numchunks * CHUNK_SIZE); | |
248 | } | |
249 | ||
fefa1800 | 250 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 251 | static int bin2bitbang(const char *filename, |
fefa1800 | 252 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 253 | { |
fefa1800 | 254 | FILE *f; |
28a35d8a HE |
255 | long file_size; |
256 | unsigned long offset = 0; | |
257 | unsigned char *p; | |
258 | uint8_t *compressed_buf, *firmware; | |
259 | uLongf csize, fwsize; | |
260 | const int buffer_size = 65536; | |
261 | size_t i; | |
fefa1800 UH |
262 | int c, ret, bit, v; |
263 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 264 | |
fefa1800 | 265 | f = fopen(filename, "r"); |
28a35d8a HE |
266 | if (!f) { |
267 | g_warning("fopen(\"%s\", \"r\")", filename); | |
268 | return -1; | |
269 | } | |
270 | ||
271 | if (-1 == fseek(f, 0, SEEK_END)) { | |
272 | g_warning("fseek on %s failed", filename); | |
273 | fclose(f); | |
274 | return -1; | |
275 | } | |
276 | ||
277 | file_size = ftell(f); | |
278 | ||
279 | fseek(f, 0, SEEK_SET); | |
280 | ||
28a35d8a HE |
281 | compressed_buf = g_malloc(file_size); |
282 | firmware = g_malloc(buffer_size); | |
283 | ||
284 | if (!compressed_buf || !firmware) { | |
285 | g_warning("Error allocating buffers"); | |
286 | return -1; | |
287 | } | |
288 | ||
28a35d8a HE |
289 | csize = 0; |
290 | while ((c = getc(f)) != EOF) { | |
291 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
292 | compressed_buf[csize++] = c ^ imm; | |
293 | } | |
294 | fclose(f); | |
295 | ||
296 | fwsize = buffer_size; | |
297 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
298 | if (ret < 0) { | |
299 | g_free(compressed_buf); | |
300 | g_free(firmware); | |
301 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
302 | return -1; | |
303 | } | |
304 | ||
305 | g_free(compressed_buf); | |
306 | ||
307 | *buf_size = fwsize * 2 * 8; | |
308 | ||
fefa1800 | 309 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
310 | |
311 | if (!p) { | |
312 | g_warning("Error allocating buffers"); | |
313 | return -1; | |
314 | } | |
315 | ||
316 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 317 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 318 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
319 | p[offset++] = v | 0x01; |
320 | p[offset++] = v; | |
321 | } | |
322 | } | |
323 | ||
324 | g_free(firmware); | |
325 | ||
326 | if (offset != *buf_size) { | |
327 | g_free(*buf); | |
328 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
329 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
330 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
331 | |
332 | return -1; | |
333 | } | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int hw_init(char *deviceinfo) | |
339 | { | |
340 | struct sigrok_device_instance *sdi; | |
341 | ||
342 | deviceinfo = deviceinfo; | |
343 | ||
344 | ftdi_init(&ftdic); | |
345 | ||
fefa1800 UH |
346 | /* Look for SIGMAs. */ |
347 | if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT, | |
348 | USB_DESCRIPTION, NULL) < 0) | |
28a35d8a HE |
349 | return 0; |
350 | ||
fefa1800 | 351 | /* Register SIGMA device. */ |
28a35d8a HE |
352 | sdi = sigrok_device_instance_new(0, ST_INITIALIZING, |
353 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
354 | if (!sdi) | |
355 | return 0; | |
356 | ||
357 | device_instances = g_slist_append(device_instances, sdi); | |
358 | ||
fefa1800 | 359 | /* We will open the device again when we need it. */ |
28a35d8a HE |
360 | ftdi_usb_close(&ftdic); |
361 | ||
362 | return 1; | |
363 | } | |
364 | ||
f6564c8d | 365 | static int upload_firmware(int firmware_idx) |
28a35d8a HE |
366 | { |
367 | int ret; | |
368 | unsigned char *buf; | |
369 | unsigned char pins; | |
370 | size_t buf_size; | |
28a35d8a | 371 | unsigned char result[32]; |
e8397563 | 372 | char firmware_path[128]; |
28a35d8a | 373 | |
fefa1800 | 374 | /* Make sure it's an ASIX SIGMA. */ |
28a35d8a HE |
375 | if ((ret = ftdi_usb_open_desc(&ftdic, |
376 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
28a35d8a | 377 | g_warning("ftdi_usb_open failed: %s", |
fefa1800 | 378 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
379 | return 0; |
380 | } | |
381 | ||
382 | if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
383 | g_warning("ftdi_set_bitmode failed: %s", | |
fefa1800 | 384 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
385 | return 0; |
386 | } | |
387 | ||
fefa1800 | 388 | /* Four times the speed of sigmalogan - Works well. */ |
28a35d8a HE |
389 | if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) { |
390 | g_warning("ftdi_set_baudrate failed: %s", | |
fefa1800 | 391 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
392 | return 0; |
393 | } | |
394 | ||
fefa1800 | 395 | /* Force the FPGA to reboot. */ |
28a35d8a HE |
396 | sigma_write(suicide, sizeof(suicide)); |
397 | sigma_write(suicide, sizeof(suicide)); | |
398 | sigma_write(suicide, sizeof(suicide)); | |
399 | sigma_write(suicide, sizeof(suicide)); | |
400 | ||
fefa1800 | 401 | /* Prepare to upload firmware (FPGA specific). */ |
28a35d8a HE |
402 | sigma_write(init, sizeof(init)); |
403 | ||
404 | ftdi_usb_purge_buffers(&ftdic); | |
405 | ||
fefa1800 | 406 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a HE |
407 | while (1) { |
408 | ret = sigma_read(result, 1); | |
409 | if (result[0] & 0x20) | |
410 | break; | |
411 | } | |
412 | ||
9ddb2a12 | 413 | /* Prepare firmware. */ |
e8397563 | 414 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
415 | firmware_files[firmware_idx]); |
416 | ||
e8397563 | 417 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 418 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 419 | firmware_path); |
28a35d8a HE |
420 | return SIGROK_ERR; |
421 | } | |
422 | ||
fefa1800 | 423 | /* Upload firmare. */ |
28a35d8a HE |
424 | sigma_write(buf, buf_size); |
425 | ||
426 | g_free(buf); | |
427 | ||
428 | if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) { | |
9ddb2a12 | 429 | g_warning("ftdi_set_bitmode failed: %s", |
fefa1800 | 430 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
431 | return SIGROK_ERR; |
432 | } | |
433 | ||
434 | ftdi_usb_purge_buffers(&ftdic); | |
435 | ||
fefa1800 | 436 | /* Discard garbage. */ |
28a35d8a HE |
437 | while (1 == sigma_read(&pins, 1)) |
438 | ; | |
439 | ||
fefa1800 | 440 | /* Initialize the logic analyzer mode. */ |
28a35d8a HE |
441 | sigma_write(logic_mode_start, sizeof(logic_mode_start)); |
442 | ||
fefa1800 | 443 | /* Expect a 3 byte reply. */ |
28a35d8a HE |
444 | ret = sigma_read(result, 3); |
445 | if (ret != 3 || | |
446 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 447 | g_warning("Configuration failed. Invalid reply received."); |
28a35d8a HE |
448 | return SIGROK_ERR; |
449 | } | |
450 | ||
f6564c8d HE |
451 | cur_firmware = firmware_idx; |
452 | ||
453 | return SIGROK_OK; | |
454 | } | |
455 | ||
456 | static int hw_opendev(int device_index) | |
457 | { | |
458 | struct sigrok_device_instance *sdi; | |
459 | int ret; | |
460 | ||
9ddb2a12 | 461 | /* Make sure it's an ASIX SIGMA. */ |
f6564c8d HE |
462 | if ((ret = ftdi_usb_open_desc(&ftdic, |
463 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
464 | ||
465 | g_warning("ftdi_usb_open failed: %s", | |
466 | ftdi_get_error_string(&ftdic)); | |
467 | ||
468 | return 0; | |
469 | } | |
28a35d8a HE |
470 | |
471 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
472 | return SIGROK_ERR; | |
473 | ||
474 | sdi->status = ST_ACTIVE; | |
475 | ||
f6564c8d HE |
476 | return SIGROK_OK; |
477 | } | |
478 | ||
479 | static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate) | |
480 | { | |
e8397563 | 481 | int i, ret; |
f6564c8d HE |
482 | |
483 | sdi = sdi; | |
484 | ||
485 | for (i = 0; supported_samplerates[i]; i++) { | |
486 | if (supported_samplerates[i] == samplerate) | |
487 | break; | |
488 | } | |
489 | if (supported_samplerates[i] == 0) | |
490 | return SIGROK_ERR_SAMPLERATE; | |
491 | ||
e8397563 HE |
492 | if (samplerate <= MHZ(50)) { |
493 | ret = upload_firmware(0); | |
f78898e9 | 494 | num_probes = 16; |
e8397563 | 495 | } |
f78898e9 | 496 | if (samplerate == MHZ(100)) { |
e8397563 | 497 | ret = upload_firmware(1); |
f78898e9 HE |
498 | num_probes = 8; |
499 | } | |
500 | else if (samplerate == MHZ(200)) { | |
e8397563 | 501 | ret = upload_firmware(2); |
f78898e9 HE |
502 | num_probes = 4; |
503 | } | |
f6564c8d | 504 | |
e8397563 | 505 | cur_samplerate = samplerate; |
f78898e9 | 506 | samples_per_event = 16 / num_probes; |
f6564c8d | 507 | |
28a35d8a HE |
508 | g_message("Firmware uploaded"); |
509 | ||
e8397563 | 510 | return ret; |
28a35d8a HE |
511 | } |
512 | ||
57bbf56b HE |
513 | /* Only trigger on single pin supported (in 100-200 MHz modes) */ |
514 | static int configure_probes(GSList *probes) | |
515 | { | |
516 | struct probe *probe; | |
517 | GSList *l; | |
518 | int trigger_set = 0; | |
519 | ||
520 | for (l = probes; l; l = l->next) { | |
521 | probe = (struct probe *)l->data; | |
522 | ||
523 | if (!probe->enabled || !probe->trigger) | |
524 | continue; | |
525 | ||
526 | if (trigger_set) { | |
527 | g_warning("Asix Sigma only supports a single pin trigger" | |
528 | " in 100 and 200 MHz mode."); | |
529 | ||
530 | return SIGROK_ERR; | |
531 | } | |
532 | ||
533 | /* Found trigger */ | |
534 | if (probe->trigger[0] == 'f') | |
535 | triggerfall = 1; | |
536 | else | |
537 | triggerfall = 0; | |
538 | ||
539 | triggerpin = probe->index - 1; | |
540 | trigger_set = 1; | |
541 | } | |
542 | ||
543 | return SIGROK_OK; | |
544 | } | |
545 | ||
28a35d8a HE |
546 | static void hw_closedev(int device_index) |
547 | { | |
548 | device_index = device_index; | |
549 | ||
550 | ftdi_usb_close(&ftdic); | |
551 | } | |
552 | ||
28a35d8a HE |
553 | static void hw_cleanup(void) |
554 | { | |
555 | } | |
556 | ||
28a35d8a HE |
557 | static void *hw_get_device_info(int device_index, int device_info_id) |
558 | { | |
559 | struct sigrok_device_instance *sdi; | |
560 | void *info = NULL; | |
561 | ||
562 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) { | |
563 | fprintf(stderr, "It's NULL.\n"); | |
564 | return NULL; | |
565 | } | |
566 | ||
567 | switch (device_info_id) { | |
568 | case DI_INSTANCE: | |
569 | info = sdi; | |
570 | break; | |
571 | case DI_NUM_PROBES: | |
edca2c5c | 572 | info = GINT_TO_POINTER(16); |
28a35d8a HE |
573 | break; |
574 | case DI_SAMPLERATES: | |
575 | info = &samplerates; | |
576 | break; | |
577 | case DI_TRIGGER_TYPES: | |
57bbf56b | 578 | info = (char *)TRIGGER_TYPES; |
28a35d8a HE |
579 | break; |
580 | case DI_CUR_SAMPLERATE: | |
581 | info = &cur_samplerate; | |
582 | break; | |
583 | } | |
584 | ||
585 | return info; | |
586 | } | |
587 | ||
28a35d8a HE |
588 | static int hw_get_status(int device_index) |
589 | { | |
590 | struct sigrok_device_instance *sdi; | |
591 | ||
592 | sdi = get_sigrok_device_instance(device_instances, device_index); | |
593 | if (sdi) | |
594 | return sdi->status; | |
595 | else | |
596 | return ST_NOT_FOUND; | |
597 | } | |
598 | ||
28a35d8a HE |
599 | static int *hw_get_capabilities(void) |
600 | { | |
601 | return capabilities; | |
602 | } | |
603 | ||
604 | static int hw_set_configuration(int device_index, int capability, void *value) | |
605 | { | |
606 | struct sigrok_device_instance *sdi; | |
607 | int ret; | |
f6564c8d | 608 | |
28a35d8a HE |
609 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) |
610 | return SIGROK_ERR; | |
611 | ||
612 | if (capability == HWCAP_SAMPLERATE) { | |
f6564c8d | 613 | ret = set_samplerate(sdi, *(uint64_t*) value); |
28a35d8a | 614 | } else if (capability == HWCAP_PROBECONFIG) { |
57bbf56b | 615 | ret = configure_probes(value); |
28a35d8a HE |
616 | } else if (capability == HWCAP_LIMIT_MSEC) { |
617 | limit_msec = strtoull(value, NULL, 10); | |
618 | ret = SIGROK_OK; | |
57bbf56b HE |
619 | } else if (capability == HWCAP_CAPTURE_RATIO) { |
620 | capture_ratio = strtoull(value, NULL, 10); | |
621 | ret = SIGROK_OK; | |
622 | } else if (capability == HWCAP_PROBECONFIG) { | |
623 | ret = configure_probes((GSList *) value); | |
28a35d8a HE |
624 | } else { |
625 | ret = SIGROK_ERR; | |
626 | } | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
28a35d8a | 631 | /* |
fefa1800 UH |
632 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
633 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
634 | * |
635 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
636 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
637 | * For 50 MHz and below, events contain one sample for each channel, | |
638 | * spread 20 ns apart. | |
28a35d8a HE |
639 | */ |
640 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
57bbf56b | 641 | uint16_t *lastsample, int triggerpos, void *user_data) |
28a35d8a | 642 | { |
fefa1800 | 643 | uint16_t tsdiff, ts; |
f78898e9 | 644 | uint16_t samples[65536 * samples_per_event]; |
28a35d8a | 645 | struct datafeed_packet packet; |
f78898e9 | 646 | int i, j, k, l, numpad, tosend; |
fefa1800 | 647 | size_t n = 0, sent = 0; |
f78898e9 | 648 | int clustersize = EVENTS_PER_CLUSTER * samples_per_event; |
fefa1800 | 649 | uint16_t *event; |
f78898e9 | 650 | uint16_t cur_sample; |
57bbf56b HE |
651 | int triggerts = -1; |
652 | ||
653 | /* Find in which cluster the trigger occured */ | |
654 | if (triggerpos != -1) | |
655 | triggerts = (triggerpos / 7); | |
28a35d8a HE |
656 | |
657 | /* For each ts */ | |
658 | for (i = 0; i < 64; ++i) { | |
fefa1800 | 659 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
660 | tsdiff = ts - *lastts; |
661 | *lastts = ts; | |
662 | ||
fefa1800 UH |
663 | /* Pad last sample up to current point. */ |
664 | numpad = tsdiff * samples_per_event - clustersize; | |
28a35d8a | 665 | if (numpad > 0) { |
f78898e9 HE |
666 | for (j = 0; j < numpad; ++j) |
667 | samples[j] = *lastsample; | |
668 | ||
669 | n = numpad; | |
28a35d8a HE |
670 | } |
671 | ||
57bbf56b HE |
672 | /* Send samples between previous and this timestamp to sigrok. */ |
673 | sent = 0; | |
674 | while (sent < n) { | |
675 | tosend = MIN(2048, n - sent); | |
676 | ||
677 | packet.type = DF_LOGIC16; | |
678 | packet.length = tosend * sizeof(uint16_t); | |
679 | packet.payload = samples + sent; | |
680 | session_bus(user_data, &packet); | |
28a35d8a | 681 | |
57bbf56b HE |
682 | sent += tosend; |
683 | } | |
684 | n = 0; | |
685 | ||
686 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
687 | cur_sample = 0; |
688 | ||
689 | /* For each event in cluster. */ | |
28a35d8a | 690 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
691 | |
692 | /* For each sample in event. */ | |
28a35d8a | 693 | for (k = 0; k < samples_per_event; ++k) { |
f78898e9 HE |
694 | cur_sample = 0; |
695 | ||
696 | /* For each probe. */ | |
697 | for (l = 0; l < num_probes; ++l) | |
edca2c5c HE |
698 | cur_sample |= (!!(event[j] & (1 << (l * |
699 | samples_per_event + k)))) | |
700 | << l; | |
f78898e9 HE |
701 | |
702 | samples[n++] = cur_sample; | |
28a35d8a HE |
703 | } |
704 | } | |
705 | ||
fefa1800 | 706 | *lastsample = samples[n - 1]; |
28a35d8a | 707 | |
57bbf56b | 708 | /* Send data up to trigger point (if triggered) */ |
fefa1800 | 709 | sent = 0; |
57bbf56b HE |
710 | if (i == triggerts) { |
711 | /* | |
712 | * Trigger is presumptively only accurate to event, i.e. | |
713 | * for 100 and 200 MHz, where multiple samples are coded | |
714 | * in a single event, the trigger does not match the | |
715 | * exact sample. | |
716 | */ | |
717 | tosend = (triggerpos % 7) - 3; | |
718 | ||
719 | if (tosend > 0) { | |
720 | packet.type = DF_LOGIC16; | |
721 | packet.length = tosend * sizeof(uint16_t); | |
722 | packet.payload = samples; | |
723 | session_bus(user_data, &packet); | |
724 | ||
725 | sent += tosend; | |
726 | } | |
28a35d8a | 727 | |
57bbf56b HE |
728 | packet.type = DF_TRIGGER; |
729 | packet.length = 0; | |
730 | packet.payload = 0; | |
28a35d8a | 731 | session_bus(user_data, &packet); |
28a35d8a | 732 | } |
57bbf56b HE |
733 | |
734 | /* Send rest of the chunk to sigrok */ | |
735 | tosend = n - sent; | |
736 | ||
737 | packet.type = DF_LOGIC16; | |
738 | packet.length = tosend * sizeof(uint16_t); | |
739 | packet.payload = samples + sent; | |
740 | session_bus(user_data, &packet); | |
28a35d8a HE |
741 | } |
742 | ||
f78898e9 | 743 | return SIGROK_OK; |
28a35d8a HE |
744 | } |
745 | ||
746 | static int receive_data(int fd, int revents, void *user_data) | |
747 | { | |
748 | struct datafeed_packet packet; | |
28a35d8a HE |
749 | const int chunks_per_read = 32; |
750 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
fefa1800 UH |
751 | int bufsz, numchunks, curchunk, i, newchunks; |
752 | uint32_t triggerpos, stoppos, running_msec; | |
28a35d8a | 753 | struct timeval tv; |
28a35d8a | 754 | uint16_t lastts = 0; |
f78898e9 | 755 | uint16_t lastsample = 0; |
57bbf56b HE |
756 | uint8_t modestatus; |
757 | int triggerchunk = -1; | |
28a35d8a HE |
758 | |
759 | fd = fd; | |
760 | revents = revents; | |
761 | ||
fefa1800 | 762 | /* Get the current position. */ |
28a35d8a HE |
763 | sigma_read_pos(&stoppos, &triggerpos); |
764 | numchunks = stoppos / 512; | |
765 | ||
fefa1800 | 766 | /* Check if the has expired, or memory is full. */ |
28a35d8a HE |
767 | gettimeofday(&tv, 0); |
768 | running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 + | |
fefa1800 | 769 | (tv.tv_usec - start_tv.tv_usec) / 1000; |
28a35d8a HE |
770 | |
771 | if (running_msec < limit_msec && numchunks < 32767) | |
772 | return FALSE; | |
773 | ||
fefa1800 | 774 | /* Stop acqusition. */ |
28a35d8a HE |
775 | sigma_set_register(WRITE_MODE, 0x11); |
776 | ||
fefa1800 | 777 | /* Set SDRAM Read Enable. */ |
28a35d8a HE |
778 | sigma_set_register(WRITE_MODE, 0x02); |
779 | ||
fefa1800 | 780 | /* Get the current position. */ |
28a35d8a HE |
781 | sigma_read_pos(&stoppos, &triggerpos); |
782 | ||
57bbf56b HE |
783 | /* Check if trigger has fired */ |
784 | modestatus = sigma_get_register(READ_MODE); | |
785 | if (modestatus & 0x20) { | |
786 | triggerchunk = triggerpos / 512; | |
787 | } | |
f78898e9 | 788 | |
fefa1800 | 789 | /* Download sample data. */ |
28a35d8a | 790 | for (curchunk = 0; curchunk < numchunks;) { |
fefa1800 | 791 | newchunks = MIN(chunks_per_read, numchunks - curchunk); |
28a35d8a HE |
792 | |
793 | g_message("Downloading sample data: %.0f %%", | |
fefa1800 | 794 | 100.0 * curchunk / numchunks); |
28a35d8a HE |
795 | |
796 | bufsz = sigma_read_dram(curchunk, newchunks, buf); | |
797 | ||
fefa1800 UH |
798 | /* Find first ts. */ |
799 | if (curchunk == 0) | |
800 | lastts = *(uint16_t *) buf - 1; | |
28a35d8a | 801 | |
fefa1800 | 802 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 803 | for (i = 0; i < newchunks; ++i) { |
57bbf56b HE |
804 | if (curchunk + i == triggerchunk) |
805 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
806 | &lastts, &lastsample, | |
807 | triggerpos & 0x1ff, user_data); | |
808 | else | |
809 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
810 | &lastts, &lastsample, | |
811 | -1, user_data); | |
28a35d8a HE |
812 | } |
813 | ||
814 | curchunk += newchunks; | |
815 | } | |
816 | ||
817 | /* End of data */ | |
818 | packet.type = DF_END; | |
819 | packet.length = 0; | |
820 | session_bus(user_data, &packet); | |
821 | ||
822 | return TRUE; | |
823 | } | |
824 | ||
825 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
826 | { | |
827 | struct sigrok_device_instance *sdi; | |
828 | struct datafeed_packet packet; | |
829 | struct datafeed_header header; | |
9ddb2a12 UH |
830 | struct clockselect_50 clockselect; |
831 | int frac; | |
57bbf56b HE |
832 | uint8_t triggerselect; |
833 | struct triggerinout triggerinout_conf; | |
28a35d8a HE |
834 | |
835 | session_device_id = session_device_id; | |
836 | ||
837 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
838 | return SIGROK_ERR; | |
839 | ||
840 | device_index = device_index; | |
841 | ||
ed09fd07 | 842 | /* If the samplerate has not been set, default to 50 MHz. */ |
9ddb2a12 | 843 | if (cur_firmware == -1) |
ed09fd07 | 844 | set_samplerate(sdi, MHZ(50)); |
e8397563 | 845 | |
57bbf56b | 846 | /* Enter trigger programming mode */ |
28a35d8a HE |
847 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); |
848 | ||
57bbf56b HE |
849 | /* 100 and 200 MHz mode */ |
850 | if (cur_samplerate >= MHZ(100)) { | |
851 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81); | |
852 | ||
853 | triggerselect = (1 << LEDSEL1) | (triggerfall << 3) | | |
854 | (triggerpin & 0x7); | |
855 | ||
856 | /* All other modes */ | |
857 | } else if (cur_samplerate <= MHZ(50)) { | |
858 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); | |
859 | ||
860 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
861 | } | |
862 | ||
863 | /* Setup trigger in and out pins to default values */ | |
864 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
865 | triggerinout_conf.trgout_bytrigger = 1; | |
866 | triggerinout_conf.trgout_enable = 1; | |
867 | ||
28a35d8a | 868 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b HE |
869 | (uint8_t *) &triggerinout_conf, |
870 | sizeof(struct triggerinout)); | |
28a35d8a | 871 | |
57bbf56b HE |
872 | /* Go back to normal mode */ |
873 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect); | |
28a35d8a | 874 | |
edca2c5c HE |
875 | /* Set clock select register. */ |
876 | if (cur_samplerate == MHZ(200)) | |
877 | /* Enable 4 probes. */ | |
878 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0); | |
879 | else if (cur_samplerate == MHZ(100)) | |
880 | /* Enable 8 probes. */ | |
881 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00); | |
882 | else { | |
883 | /* | |
9ddb2a12 UH |
884 | * 50 MHz mode (or fraction thereof). Any fraction down to |
885 | * 50 MHz / 256 can be used, but is not suppoted by sigrok API. | |
edca2c5c | 886 | */ |
9ddb2a12 | 887 | frac = MHZ(50) / cur_samplerate - 1; |
edca2c5c | 888 | |
9ddb2a12 UH |
889 | clockselect.async = 0; |
890 | clockselect.fraction = frac; | |
891 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
892 | |
893 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 UH |
894 | (uint8_t *) &clockselect, |
895 | sizeof(clockselect)); | |
edca2c5c HE |
896 | } |
897 | ||
fefa1800 | 898 | /* Setup maximum post trigger time. */ |
57bbf56b | 899 | sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 256) / 100); |
28a35d8a | 900 | |
fefa1800 | 901 | /* Start acqusition (software trigger start). */ |
28a35d8a HE |
902 | gettimeofday(&start_tv, 0); |
903 | sigma_set_register(WRITE_MODE, 0x0d); | |
904 | ||
28a35d8a HE |
905 | /* Send header packet to the session bus. */ |
906 | packet.type = DF_HEADER; | |
907 | packet.length = sizeof(struct datafeed_header); | |
908 | packet.payload = &header; | |
909 | header.feed_version = 1; | |
910 | gettimeofday(&header.starttime, NULL); | |
911 | header.samplerate = cur_samplerate; | |
912 | header.protocol_id = PROTO_RAW; | |
edca2c5c | 913 | header.num_probes = num_probes; |
28a35d8a HE |
914 | session_bus(session_device_id, &packet); |
915 | ||
57bbf56b HE |
916 | /* Add capture source. */ |
917 | source_add(0, G_IO_IN, 10, receive_data, session_device_id); | |
918 | ||
28a35d8a HE |
919 | return SIGROK_OK; |
920 | } | |
921 | ||
28a35d8a HE |
922 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
923 | { | |
924 | device_index = device_index; | |
925 | session_device_id = session_device_id; | |
926 | ||
fefa1800 | 927 | /* Stop acquisition. */ |
28a35d8a HE |
928 | sigma_set_register(WRITE_MODE, 0x11); |
929 | ||
930 | // XXX Set some state to indicate that data should be sent to sigrok | |
931 | // Now, we just wait for timeout | |
932 | } | |
933 | ||
28a35d8a HE |
934 | struct device_plugin asix_sigma_plugin_info = { |
935 | "asix-sigma", | |
936 | 1, | |
937 | hw_init, | |
938 | hw_cleanup, | |
28a35d8a HE |
939 | hw_opendev, |
940 | hw_closedev, | |
941 | hw_get_device_info, | |
942 | hw_get_status, | |
943 | hw_get_capabilities, | |
944 | hw_set_configuration, | |
945 | hw_start_acquisition, | |
9ddb2a12 | 946 | hw_stop_acquisition, |
28a35d8a | 947 | }; |