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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a | 28 | |
b1648dea | 29 | /* |
b65649f6 GS |
30 | * The ASIX SIGMA hardware supports fixed 200MHz and 100MHz sample rates |
31 | * (by means of separate firmware images). As well as 50MHz divided by | |
32 | * an integer divider in the 1..256 range (by the "typical" firmware). | |
33 | * Which translates to a strict lower boundary of around 195kHz. | |
34 | * | |
35 | * This driver "suggests" a subset of the available rates by listing a | |
36 | * few discrete values, while setter routines accept any user specified | |
37 | * rate that is supported by the hardware. | |
b1648dea | 38 | */ |
3ba56876 | 39 | SR_PRIV const uint64_t samplerates[] = { |
b65649f6 GS |
40 | /* 50MHz and integer divider. 1/2/5 steps (where possible). */ |
41 | SR_KHZ(200), SR_KHZ(500), | |
42 | SR_MHZ(1), SR_MHZ(2), SR_MHZ(5), | |
43 | SR_MHZ(10), SR_MHZ(25), SR_MHZ(50), | |
44 | /* 100MHz/200MHz, fixed rates in special firmware. */ | |
45 | SR_MHZ(100), SR_MHZ(200), | |
28a35d8a HE |
46 | }; |
47 | ||
4154a516 | 48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); |
39c64c6a | 49 | |
742368a2 | 50 | static const char *firmware_files[] = { |
80e717b3 GS |
51 | [SIGMA_FW_50MHZ] = "asix-sigma-50.fw", /* 50MHz, 8bit divider. */ |
52 | [SIGMA_FW_100MHZ] = "asix-sigma-100.fw", /* 100MHz, fixed. */ | |
53 | [SIGMA_FW_200MHZ] = "asix-sigma-200.fw", /* 200MHz, fixed. */ | |
54 | [SIGMA_FW_SYNC] = "asix-sigma-50sync.fw", /* Sync from external pin. */ | |
55 | [SIGMA_FW_FREQ] = "asix-sigma-phasor.fw", /* Frequency counter. */ | |
f6564c8d HE |
56 | }; |
57 | ||
742368a2 GS |
58 | #define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024) |
59 | ||
9b4d261f | 60 | static int sigma_read(struct dev_context *devc, void *buf, size_t size) |
28a35d8a HE |
61 | { |
62 | int ret; | |
fefa1800 | 63 | |
0e1357e8 | 64 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 65 | if (ret < 0) { |
47f4f073 | 66 | sr_err("ftdi_read_data failed: %s", |
9b4d261f | 67 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
68 | } |
69 | ||
70 | return ret; | |
71 | } | |
72 | ||
a53b8e4d | 73 | static int sigma_write(struct dev_context *devc, const void *buf, size_t size) |
28a35d8a HE |
74 | { |
75 | int ret; | |
fefa1800 | 76 | |
a53b8e4d | 77 | ret = ftdi_write_data(&devc->ftdic, buf, size); |
8ebad343 | 78 | if (ret < 0) |
47f4f073 | 79 | sr_err("ftdi_write_data failed: %s", |
9b4d261f | 80 | ftdi_get_error_string(&devc->ftdic)); |
8ebad343 | 81 | else if ((size_t) ret != size) |
47f4f073 | 82 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
83 | |
84 | return ret; | |
85 | } | |
86 | ||
e8686e3a AG |
87 | /* |
88 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
89 | * device. We still print a message just in case. | |
90 | */ | |
9b4d261f GS |
91 | SR_PRIV int sigma_write_register(struct dev_context *devc, |
92 | uint8_t reg, uint8_t *data, size_t len) | |
28a35d8a | 93 | { |
a53b8e4d GS |
94 | uint8_t buf[80], *wrptr; |
95 | size_t idx, count; | |
96 | int ret; | |
28a35d8a | 97 | |
a53b8e4d | 98 | if (2 + 2 * len > sizeof(buf)) { |
9b4d261f | 99 | sr_err("Write buffer too small to write %zu bytes.", len); |
e8686e3a AG |
100 | return SR_ERR_BUG; |
101 | } | |
102 | ||
a53b8e4d GS |
103 | wrptr = buf; |
104 | write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf)); | |
105 | write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4)); | |
106 | for (idx = 0; idx < len; idx++) { | |
107 | write_u8_inc(&wrptr, REG_DATA_LOW | (data[idx] & 0xf)); | |
108 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data[idx] >> 4)); | |
28a35d8a | 109 | } |
a53b8e4d GS |
110 | count = wrptr - buf; |
111 | ret = sigma_write(devc, buf, count); | |
112 | if (ret != SR_OK) | |
113 | return ret; | |
28a35d8a | 114 | |
a53b8e4d | 115 | return SR_OK; |
28a35d8a HE |
116 | } |
117 | ||
9b4d261f GS |
118 | SR_PRIV int sigma_set_register(struct dev_context *devc, |
119 | uint8_t reg, uint8_t value) | |
28a35d8a | 120 | { |
9b4d261f | 121 | return sigma_write_register(devc, reg, &value, sizeof(value)); |
28a35d8a HE |
122 | } |
123 | ||
9b4d261f GS |
124 | static int sigma_read_register(struct dev_context *devc, |
125 | uint8_t reg, uint8_t *data, size_t len) | |
28a35d8a | 126 | { |
a53b8e4d | 127 | uint8_t buf[3], *wrptr; |
28a35d8a | 128 | |
a53b8e4d GS |
129 | wrptr = buf; |
130 | write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf)); | |
131 | write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4)); | |
132 | write_u8_inc(&wrptr, REG_READ_ADDR); | |
133 | sigma_write(devc, buf, wrptr - buf); | |
28a35d8a | 134 | |
9b4d261f | 135 | return sigma_read(devc, data, len); |
28a35d8a HE |
136 | } |
137 | ||
9b4d261f GS |
138 | static int sigma_read_pos(struct dev_context *devc, |
139 | uint32_t *stoppos, uint32_t *triggerpos) | |
28a35d8a | 140 | { |
07411a60 GS |
141 | /* |
142 | * Read 6 registers starting at trigger position LSB. | |
143 | * Which yields two 24bit counter values. | |
144 | */ | |
a53b8e4d | 145 | const uint8_t buf[] = { |
28a35d8a | 146 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, |
07411a60 GS |
147 | REG_READ_ADDR | REG_ADDR_INC, |
148 | REG_READ_ADDR | REG_ADDR_INC, | |
149 | REG_READ_ADDR | REG_ADDR_INC, | |
150 | REG_READ_ADDR | REG_ADDR_INC, | |
151 | REG_READ_ADDR | REG_ADDR_INC, | |
152 | REG_READ_ADDR | REG_ADDR_INC, | |
a53b8e4d | 153 | }, *rdptr; |
28a35d8a HE |
154 | uint8_t result[6]; |
155 | ||
9b4d261f | 156 | sigma_write(devc, buf, sizeof(buf)); |
28a35d8a | 157 | |
9b4d261f | 158 | sigma_read(devc, result, sizeof(result)); |
28a35d8a | 159 | |
a53b8e4d GS |
160 | rdptr = &result[0]; |
161 | *triggerpos = read_u24le_inc(&rdptr); | |
162 | *stoppos = read_u24le_inc(&rdptr); | |
28a35d8a | 163 | |
dc400817 | 164 | /* |
a53b8e4d GS |
165 | * These positions consist of "the memory row" in the MSB fields, |
166 | * and "an event index" within the row in the LSB fields. Part | |
167 | * of the memory row's content is sample data, another part is | |
168 | * timestamps. | |
2c33b092 | 169 | * |
a53b8e4d GS |
170 | * The retrieved register values point to after the captured |
171 | * position. So they need to get decremented, and adjusted to | |
172 | * cater for the timestamps when the decrement carries over to | |
173 | * a different memory row. | |
dc400817 | 174 | */ |
a53b8e4d GS |
175 | if ((--*stoppos & ROW_MASK) == ROW_MASK) |
176 | *stoppos -= CLUSTERS_PER_ROW; | |
177 | if ((--*triggerpos & ROW_MASK) == ROW_MASK) | |
178 | *triggerpos -= CLUSTERS_PER_ROW; | |
57bbf56b | 179 | |
a53b8e4d | 180 | return SR_OK; |
28a35d8a HE |
181 | } |
182 | ||
9b4d261f GS |
183 | static int sigma_read_dram(struct dev_context *devc, |
184 | uint16_t startchunk, size_t numchunks, uint8_t *data) | |
28a35d8a | 185 | { |
a53b8e4d | 186 | uint8_t buf[128], *wrptr; |
07411a60 GS |
187 | size_t chunk; |
188 | int sel; | |
189 | gboolean is_last; | |
28a35d8a | 190 | |
a53b8e4d GS |
191 | if (2 + 3 * numchunks > ARRAY_SIZE(buf)) { |
192 | sr_err("Read buffer too small to read %zu DRAM rows", numchunks); | |
193 | return SR_ERR_BUG; | |
194 | } | |
195 | ||
07411a60 | 196 | /* Communicate DRAM start address (memory row, aka samples line). */ |
a53b8e4d GS |
197 | wrptr = buf; |
198 | write_u8_inc(&wrptr, startchunk >> 8); | |
199 | write_u8_inc(&wrptr, startchunk & 0xff); | |
200 | sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf); | |
28a35d8a | 201 | |
07411a60 GS |
202 | /* |
203 | * Access DRAM content. Fetch from DRAM to FPGA's internal RAM, | |
204 | * then transfer via USB. Interleave the FPGA's DRAM access and | |
205 | * USB transfer, use alternating buffers (0/1) in the process. | |
206 | */ | |
a53b8e4d GS |
207 | wrptr = buf; |
208 | write_u8_inc(&wrptr, REG_DRAM_BLOCK); | |
209 | write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK); | |
07411a60 GS |
210 | for (chunk = 0; chunk < numchunks; chunk++) { |
211 | sel = chunk % 2; | |
212 | is_last = chunk == numchunks - 1; | |
213 | if (!is_last) | |
a53b8e4d GS |
214 | write_u8_inc(&wrptr, REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel)); |
215 | write_u8_inc(&wrptr, REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel)); | |
07411a60 | 216 | if (!is_last) |
a53b8e4d | 217 | write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK); |
28a35d8a | 218 | } |
a53b8e4d | 219 | sigma_write(devc, buf, wrptr - buf); |
28a35d8a | 220 | |
9b4d261f | 221 | return sigma_read(devc, data, numchunks * ROW_LENGTH_BYTES); |
28a35d8a HE |
222 | } |
223 | ||
4ae1f451 | 224 | /* Upload trigger look-up tables to Sigma. */ |
9b4d261f GS |
225 | SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, |
226 | struct triggerlut *lut) | |
ee492173 HE |
227 | { |
228 | int i; | |
229 | uint8_t tmp[2]; | |
230 | uint16_t bit; | |
a53b8e4d | 231 | uint8_t buf[6], *wrptr, regval; |
ee492173 HE |
232 | |
233 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 234 | for (i = 0; i < 16; i++) { |
ee492173 HE |
235 | bit = 1 << i; |
236 | ||
237 | tmp[0] = tmp[1] = 0; | |
238 | ||
239 | if (lut->m2d[0] & bit) | |
240 | tmp[0] |= 0x01; | |
241 | if (lut->m2d[1] & bit) | |
242 | tmp[0] |= 0x02; | |
243 | if (lut->m2d[2] & bit) | |
244 | tmp[0] |= 0x04; | |
245 | if (lut->m2d[3] & bit) | |
246 | tmp[0] |= 0x08; | |
247 | ||
248 | if (lut->m3 & bit) | |
249 | tmp[0] |= 0x10; | |
250 | if (lut->m3s & bit) | |
251 | tmp[0] |= 0x20; | |
252 | if (lut->m4 & bit) | |
253 | tmp[0] |= 0x40; | |
254 | ||
255 | if (lut->m0d[0] & bit) | |
256 | tmp[1] |= 0x01; | |
257 | if (lut->m0d[1] & bit) | |
258 | tmp[1] |= 0x02; | |
259 | if (lut->m0d[2] & bit) | |
260 | tmp[1] |= 0x04; | |
261 | if (lut->m0d[3] & bit) | |
262 | tmp[1] |= 0x08; | |
263 | ||
264 | if (lut->m1d[0] & bit) | |
265 | tmp[1] |= 0x10; | |
266 | if (lut->m1d[1] & bit) | |
267 | tmp[1] |= 0x20; | |
268 | if (lut->m1d[2] & bit) | |
269 | tmp[1] |= 0x40; | |
270 | if (lut->m1d[3] & bit) | |
271 | tmp[1] |= 0x80; | |
272 | ||
a53b8e4d GS |
273 | /* |
274 | * This logic seems redundant, but separates the value | |
275 | * determination from the wire format, and is useful | |
276 | * during future maintenance and research. | |
277 | */ | |
278 | wrptr = buf; | |
279 | write_u8_inc(&wrptr, tmp[0]); | |
280 | write_u8_inc(&wrptr, tmp[1]); | |
281 | sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); | |
9b4d261f | 282 | sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x30 | i); |
ee492173 HE |
283 | } |
284 | ||
285 | /* Send the parameters */ | |
a53b8e4d GS |
286 | wrptr = buf; |
287 | regval = 0; | |
288 | regval |= lut->params.selc << 6; | |
289 | regval |= lut->params.selpresc << 0; | |
290 | write_u8_inc(&wrptr, regval); | |
291 | regval = 0; | |
292 | regval |= lut->params.selinc << 6; | |
293 | regval |= lut->params.selres << 4; | |
294 | regval |= lut->params.sela << 2; | |
295 | regval |= lut->params.selb << 0; | |
296 | write_u8_inc(&wrptr, regval); | |
297 | write_u16le_inc(&wrptr, lut->params.cmpb); | |
298 | write_u16le_inc(&wrptr, lut->params.cmpa); | |
299 | sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); | |
ee492173 | 300 | |
e46b8fb1 | 301 | return SR_OK; |
ee492173 HE |
302 | } |
303 | ||
d5fa188a | 304 | /* |
dc0906e2 GS |
305 | * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device |
306 | * uses FTDI bitbang mode for netlist download in slave serial mode. | |
307 | * (LATER: The OMEGA device's cable contains a more capable FTDI chip | |
308 | * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245 | |
309 | * compatible bitbang mode? For maximum code re-use and reduced libftdi | |
310 | * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2 | |
311 | * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.) | |
312 | * | |
313 | * 750kbps rate (four times the speed of sigmalogan) works well for | |
314 | * netlist download. All pins except INIT_B are output pins during | |
315 | * configuration download. | |
316 | * | |
317 | * Some pins are inverted as a byproduct of level shifting circuitry. | |
318 | * That's why high CCLK level (from the cable's point of view) is idle | |
319 | * from the FPGA's perspective. | |
320 | * | |
321 | * The vendor's literature discusses a "suicide sequence" which ends | |
322 | * regular FPGA execution and should be sent before entering bitbang | |
323 | * mode and sending configuration data. Set D7 and toggle D2, D3, D4 | |
324 | * a few times. | |
325 | */ | |
326 | #define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ | |
327 | #define BB_PIN_PROG (1 << 1) /* D1, PROG */ | |
328 | #define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ | |
329 | #define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ | |
330 | #define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ | |
331 | #define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ | |
332 | #define BB_PIN_DIN (1 << 6) /* D6, DIN */ | |
333 | #define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ | |
334 | ||
335 | #define BB_BITRATE (750 * 1000) | |
336 | #define BB_PINMASK (0xff & ~BB_PIN_INIT) | |
337 | ||
338 | /* | |
339 | * Initiate slave serial mode for configuration download. Which is done | |
340 | * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before | |
c749d1ca GS |
341 | * initiating the configuration download. |
342 | * | |
343 | * Run a "suicide sequence" first to terminate the regular FPGA operation | |
344 | * before reconfiguration. The FTDI cable is single channel, and shares | |
345 | * pins which are used for data communication in FIFO mode with pins that | |
346 | * are used for FPGA configuration in bitbang mode. Hardware defaults for | |
347 | * unconfigured hardware, and runtime conditions after FPGA configuration | |
348 | * need to cooperate such that re-configuration of the FPGA can start. | |
d5fa188a | 349 | */ |
c749d1ca | 350 | static int sigma_fpga_init_bitbang_once(struct dev_context *devc) |
d5fa188a | 351 | { |
a53b8e4d | 352 | const uint8_t suicide[] = { |
dc0906e2 GS |
353 | BB_PIN_D7 | BB_PIN_D2, |
354 | BB_PIN_D7 | BB_PIN_D2, | |
355 | BB_PIN_D7 | BB_PIN_D3, | |
356 | BB_PIN_D7 | BB_PIN_D2, | |
357 | BB_PIN_D7 | BB_PIN_D3, | |
358 | BB_PIN_D7 | BB_PIN_D2, | |
359 | BB_PIN_D7 | BB_PIN_D3, | |
360 | BB_PIN_D7 | BB_PIN_D2, | |
d5fa188a | 361 | }; |
a53b8e4d | 362 | const uint8_t init_array[] = { |
dc0906e2 GS |
363 | BB_PIN_CCLK, |
364 | BB_PIN_CCLK | BB_PIN_PROG, | |
365 | BB_PIN_CCLK | BB_PIN_PROG, | |
366 | BB_PIN_CCLK, | |
367 | BB_PIN_CCLK, | |
368 | BB_PIN_CCLK, | |
369 | BB_PIN_CCLK, | |
370 | BB_PIN_CCLK, | |
371 | BB_PIN_CCLK, | |
372 | BB_PIN_CCLK, | |
d5fa188a | 373 | }; |
dc0906e2 | 374 | int retries, ret; |
d5fa188a MV |
375 | uint8_t data; |
376 | ||
377 | /* Section 2. part 1), do the FPGA suicide. */ | |
9b4d261f GS |
378 | sigma_write(devc, suicide, sizeof(suicide)); |
379 | sigma_write(devc, suicide, sizeof(suicide)); | |
380 | sigma_write(devc, suicide, sizeof(suicide)); | |
381 | sigma_write(devc, suicide, sizeof(suicide)); | |
c749d1ca | 382 | g_usleep(10 * 1000); |
d5fa188a | 383 | |
dc0906e2 | 384 | /* Section 2. part 2), pulse PROG. */ |
9b4d261f | 385 | sigma_write(devc, init_array, sizeof(init_array)); |
c749d1ca | 386 | g_usleep(10 * 1000); |
d5fa188a MV |
387 | ftdi_usb_purge_buffers(&devc->ftdic); |
388 | ||
dc0906e2 GS |
389 | /* Wait until the FPGA asserts INIT_B. */ |
390 | retries = 10; | |
391 | while (retries--) { | |
a53b8e4d | 392 | ret = sigma_read(devc, &data, sizeof(data)); |
d5fa188a MV |
393 | if (ret < 0) |
394 | return ret; | |
dc0906e2 GS |
395 | if (data & BB_PIN_INIT) |
396 | return SR_OK; | |
1a46cc62 | 397 | g_usleep(10 * 1000); |
d5fa188a MV |
398 | } |
399 | ||
400 | return SR_ERR_TIMEOUT; | |
401 | } | |
402 | ||
c749d1ca GS |
403 | /* |
404 | * This is belt and braces. Re-run the bitbang initiation sequence a few | |
405 | * times should first attempts fail. Failure is rare but can happen (was | |
406 | * observed during driver development). | |
407 | */ | |
408 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
409 | { | |
410 | size_t retries; | |
411 | int ret; | |
412 | ||
413 | retries = 10; | |
414 | while (retries--) { | |
415 | ret = sigma_fpga_init_bitbang_once(devc); | |
416 | if (ret == SR_OK) | |
417 | return ret; | |
418 | if (ret != SR_ERR_TIMEOUT) | |
419 | return ret; | |
420 | } | |
421 | return ret; | |
422 | } | |
423 | ||
64fe661b MV |
424 | /* |
425 | * Configure the FPGA for logic-analyzer mode. | |
426 | */ | |
427 | static int sigma_fpga_init_la(struct dev_context *devc) | |
428 | { | |
a53b8e4d GS |
429 | uint8_t buf[16], *wrptr; |
430 | uint8_t data_55, data_aa, mode; | |
64fe661b | 431 | uint8_t result[3]; |
a53b8e4d | 432 | const uint8_t *rdptr; |
64fe661b MV |
433 | int ret; |
434 | ||
a53b8e4d GS |
435 | wrptr = buf; |
436 | ||
437 | /* Read ID register. */ | |
438 | write_u8_inc(&wrptr, REG_ADDR_LOW | (READ_ID & 0xf)); | |
439 | write_u8_inc(&wrptr, REG_ADDR_HIGH | (READ_ID >> 4)); | |
440 | write_u8_inc(&wrptr, REG_READ_ADDR); | |
441 | ||
442 | /* Write 0x55 to scratch register, read back. */ | |
443 | data_55 = 0x55; | |
444 | write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf)); | |
445 | write_u8_inc(&wrptr, REG_DATA_LOW | (data_55 & 0xf)); | |
446 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_55 >> 4)); | |
447 | write_u8_inc(&wrptr, REG_READ_ADDR); | |
448 | ||
449 | /* Write 0xaa to scratch register, read back. */ | |
450 | data_aa = 0xaa; | |
451 | write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf)); | |
452 | write_u8_inc(&wrptr, REG_DATA_LOW | (data_aa & 0xf)); | |
453 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_aa >> 4)); | |
454 | write_u8_inc(&wrptr, REG_READ_ADDR); | |
455 | ||
456 | /* Initiate SDRAM initialization in mode register. */ | |
457 | mode = WMR_SDRAMINIT; | |
458 | write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_MODE & 0xf)); | |
459 | write_u8_inc(&wrptr, REG_DATA_LOW | (mode & 0xf)); | |
460 | write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (mode >> 4)); | |
461 | ||
dc0906e2 GS |
462 | /* |
463 | * Send the command sequence which contains 3 READ requests. | |
464 | * Expect to see the corresponding 3 response bytes. | |
465 | */ | |
a53b8e4d | 466 | sigma_write(devc, buf, wrptr - buf); |
9b4d261f | 467 | ret = sigma_read(devc, result, ARRAY_SIZE(result)); |
a53b8e4d GS |
468 | if (ret != ARRAY_SIZE(result)) { |
469 | sr_err("Insufficient start response length."); | |
470 | return SR_ERR_IO; | |
471 | } | |
472 | rdptr = result; | |
473 | if (read_u8_inc(&rdptr) != 0xa6) { | |
474 | sr_err("Unexpected ID response."); | |
475 | return SR_ERR_DATA; | |
476 | } | |
477 | if (read_u8_inc(&rdptr) != data_55) { | |
478 | sr_err("Unexpected scratch read-back (55)."); | |
479 | return SR_ERR_DATA; | |
480 | } | |
481 | if (read_u8_inc(&rdptr) != data_aa) { | |
482 | sr_err("Unexpected scratch read-back (aa)."); | |
483 | return SR_ERR_DATA; | |
484 | } | |
64fe661b MV |
485 | |
486 | return SR_OK; | |
64fe661b MV |
487 | } |
488 | ||
a80226bb MV |
489 | /* |
490 | * Read the firmware from a file and transform it into a series of bitbang | |
491 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
492 | * by the caller of this function. | |
493 | */ | |
8e2d6c9d | 494 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
9b4d261f | 495 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
a80226bb | 496 | { |
dc0906e2 GS |
497 | uint8_t *firmware; |
498 | size_t file_size; | |
499 | uint8_t *p; | |
500 | size_t l; | |
a80226bb | 501 | uint32_t imm; |
dc0906e2 GS |
502 | size_t bb_size; |
503 | uint8_t *bb_stream, *bbs, byte, mask, v; | |
a80226bb | 504 | |
387825dc | 505 | /* Retrieve the on-disk firmware file content. */ |
742368a2 GS |
506 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name, |
507 | &file_size, SIGMA_FIRMWARE_SIZE_LIMIT); | |
8e2d6c9d | 508 | if (!firmware) |
dc0906e2 | 509 | return SR_ERR_IO; |
a80226bb | 510 | |
387825dc | 511 | /* Unscramble the file content (XOR with "random" sequence). */ |
dc0906e2 GS |
512 | p = firmware; |
513 | l = file_size; | |
a80226bb | 514 | imm = 0x3f6df2ab; |
dc0906e2 | 515 | while (l--) { |
a80226bb | 516 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); |
dc0906e2 | 517 | *p++ ^= imm & 0xff; |
a80226bb MV |
518 | } |
519 | ||
520 | /* | |
387825dc GS |
521 | * Generate a sequence of bitbang samples. With two samples per |
522 | * FPGA configuration bit, providing the level for the DIN signal | |
523 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
524 | * ("slave serial" mode). | |
525 | * | |
526 | * Note that CCLK is inverted in hardware. That's why the | |
527 | * respective bit is first set and then cleared in the bitbang | |
528 | * sample sets. So that the DIN level will be stable when the | |
529 | * data gets sampled at the rising CCLK edge, and the signals' | |
530 | * setup time constraint will be met. | |
531 | * | |
532 | * The caller will put the FPGA into download mode, will send | |
533 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 534 | */ |
a80226bb | 535 | bb_size = file_size * 8 * 2; |
dc0906e2 | 536 | bb_stream = g_try_malloc(bb_size); |
a80226bb MV |
537 | if (!bb_stream) { |
538 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
dc0906e2 GS |
539 | g_free(firmware); |
540 | return SR_ERR_MALLOC; | |
a80226bb | 541 | } |
a80226bb | 542 | bbs = bb_stream; |
dc0906e2 GS |
543 | p = firmware; |
544 | l = file_size; | |
545 | while (l--) { | |
546 | byte = *p++; | |
547 | mask = 0x80; | |
548 | while (mask) { | |
549 | v = (byte & mask) ? BB_PIN_DIN : 0; | |
550 | mask >>= 1; | |
551 | *bbs++ = v | BB_PIN_CCLK; | |
a80226bb MV |
552 | *bbs++ = v; |
553 | } | |
554 | } | |
dc0906e2 | 555 | g_free(firmware); |
a80226bb MV |
556 | |
557 | /* The transformation completed successfully, return the result. */ | |
558 | *bb_cmd = bb_stream; | |
559 | *bb_cmd_size = bb_size; | |
560 | ||
dc0906e2 | 561 | return SR_OK; |
a80226bb MV |
562 | } |
563 | ||
9b4d261f GS |
564 | static int upload_firmware(struct sr_context *ctx, struct dev_context *devc, |
565 | enum sigma_firmware_idx firmware_idx) | |
28a35d8a HE |
566 | { |
567 | int ret; | |
a53b8e4d GS |
568 | uint8_t *buf; |
569 | uint8_t pins; | |
28a35d8a | 570 | size_t buf_size; |
a9016883 | 571 | const char *firmware; |
a9016883 | 572 | |
80e717b3 GS |
573 | /* Check for valid firmware file selection. */ |
574 | if (firmware_idx >= ARRAY_SIZE(firmware_files)) | |
575 | return SR_ERR_ARG; | |
4b25cbff | 576 | firmware = firmware_files[firmware_idx]; |
80e717b3 GS |
577 | if (!firmware || !*firmware) |
578 | return SR_ERR_ARG; | |
579 | ||
580 | /* Avoid downloading the same firmware multiple times. */ | |
581 | if (devc->firmware_idx == firmware_idx) { | |
a9016883 GS |
582 | sr_info("Not uploading firmware file '%s' again.", firmware); |
583 | return SR_OK; | |
584 | } | |
28a35d8a | 585 | |
1bb9dc82 GS |
586 | devc->state.state = SIGMA_CONFIG; |
587 | ||
dc0906e2 GS |
588 | /* Set the cable to bitbang mode. */ |
589 | ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG); | |
8bbf7627 | 590 | if (ret < 0) { |
47f4f073 | 591 | sr_err("ftdi_set_bitmode failed: %s", |
9b4d261f | 592 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 593 | return SR_ERR; |
28a35d8a | 594 | } |
dc0906e2 | 595 | ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE); |
8bbf7627 | 596 | if (ret < 0) { |
47f4f073 | 597 | sr_err("ftdi_set_baudrate failed: %s", |
9b4d261f | 598 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 599 | return SR_ERR; |
28a35d8a HE |
600 | } |
601 | ||
dc0906e2 | 602 | /* Initiate FPGA configuration mode. */ |
d5fa188a MV |
603 | ret = sigma_fpga_init_bitbang(devc); |
604 | if (ret) | |
605 | return ret; | |
28a35d8a | 606 | |
dc0906e2 | 607 | /* Prepare wire format of the firmware image. */ |
8e2d6c9d | 608 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 609 | if (ret != SR_OK) { |
9b4d261f | 610 | sr_err("Could not prepare file %s for download.", firmware); |
b53738ba | 611 | return ret; |
28a35d8a HE |
612 | } |
613 | ||
dc0906e2 | 614 | /* Write the FPGA netlist to the cable. */ |
499b17e9 | 615 | sr_info("Uploading firmware file '%s'.", firmware); |
9b4d261f | 616 | sigma_write(devc, buf, buf_size); |
28a35d8a HE |
617 | |
618 | g_free(buf); | |
619 | ||
dc0906e2 GS |
620 | /* Leave bitbang mode and discard pending input data. */ |
621 | ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET); | |
8bbf7627 | 622 | if (ret < 0) { |
47f4f073 | 623 | sr_err("ftdi_set_bitmode failed: %s", |
9b4d261f | 624 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 625 | return SR_ERR; |
28a35d8a | 626 | } |
1f4f98e0 | 627 | ftdi_usb_purge_buffers(&devc->ftdic); |
a53b8e4d | 628 | while (sigma_read(devc, &pins, sizeof(pins)) > 0) |
28a35d8a HE |
629 | ; |
630 | ||
64fe661b MV |
631 | /* Initialize the FPGA for logic-analyzer mode. */ |
632 | ret = sigma_fpga_init_la(devc); | |
633 | if (ret != SR_OK) | |
634 | return ret; | |
28a35d8a | 635 | |
dc0906e2 | 636 | /* Keep track of successful firmware download completion. */ |
1bb9dc82 | 637 | devc->state.state = SIGMA_IDLE; |
80e717b3 | 638 | devc->firmware_idx = firmware_idx; |
47f4f073 | 639 | sr_info("Firmware uploaded."); |
e3fff420 | 640 | |
e46b8fb1 | 641 | return SR_OK; |
f6564c8d HE |
642 | } |
643 | ||
9a0a606a | 644 | /* |
5e78a564 GS |
645 | * The driver supports user specified time or sample count limits. The |
646 | * device's hardware supports neither, and hardware compression prevents | |
647 | * reliable detection of "fill levels" (currently reached sample counts) | |
648 | * from register values during acquisition. That's why the driver needs | |
649 | * to apply some heuristics: | |
9a0a606a | 650 | * |
5e78a564 GS |
651 | * - The (optional) sample count limit and the (normalized) samplerate |
652 | * get mapped to an estimated duration for these samples' acquisition. | |
653 | * - The (optional) time limit gets checked as well. The lesser of the | |
654 | * two limits will terminate the data acquisition phase. The exact | |
655 | * sample count limit gets enforced in session feed submission paths. | |
656 | * - Some slack needs to be given to account for hardware pipelines as | |
657 | * well as late storage of last chunks after compression thresholds | |
658 | * are tripped. The resulting data set will span at least the caller | |
659 | * specified period of time, which shall be perfectly acceptable. | |
660 | * | |
661 | * With RLE compression active, up to 64K sample periods can pass before | |
662 | * a cluster accumulates. Which translates to 327ms at 200kHz. Add two | |
663 | * times that period for good measure, one is not enough to flush the | |
664 | * hardware pipeline (observation from an earlier experiment). | |
9a0a606a | 665 | */ |
5e78a564 | 666 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) |
9a0a606a | 667 | { |
5e78a564 GS |
668 | int ret; |
669 | GVariant *data; | |
670 | uint64_t user_count, user_msecs; | |
9a0a606a | 671 | uint64_t worst_cluster_time_ms; |
5e78a564 | 672 | uint64_t count_msecs, acquire_msecs; |
9a0a606a | 673 | |
5e78a564 GS |
674 | sr_sw_limits_init(&devc->acq_limits); |
675 | ||
676 | /* Get sample count limit, convert to msecs. */ | |
677 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
678 | SR_CONF_LIMIT_SAMPLES, &data); | |
679 | if (ret != SR_OK) | |
680 | return ret; | |
681 | user_count = g_variant_get_uint64(data); | |
682 | g_variant_unref(data); | |
683 | count_msecs = 0; | |
684 | if (user_count) | |
685 | count_msecs = 1000 * user_count / devc->samplerate + 1; | |
686 | ||
687 | /* Get time limit, which is in msecs. */ | |
688 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
689 | SR_CONF_LIMIT_MSEC, &data); | |
690 | if (ret != SR_OK) | |
691 | return ret; | |
692 | user_msecs = g_variant_get_uint64(data); | |
693 | g_variant_unref(data); | |
694 | ||
695 | /* Get the lesser of them, with both being optional. */ | |
696 | acquire_msecs = ~0ull; | |
697 | if (user_count && count_msecs < acquire_msecs) | |
698 | acquire_msecs = count_msecs; | |
699 | if (user_msecs && user_msecs < acquire_msecs) | |
700 | acquire_msecs = user_msecs; | |
701 | if (acquire_msecs == ~0ull) | |
702 | return SR_OK; | |
703 | ||
704 | /* Add some slack, and use that timeout for acquisition. */ | |
705 | worst_cluster_time_ms = 1000 * 65536 / devc->samplerate; | |
706 | acquire_msecs += 2 * worst_cluster_time_ms; | |
707 | data = g_variant_new_uint64(acquire_msecs); | |
708 | ret = sr_sw_limits_config_set(&devc->acq_limits, | |
709 | SR_CONF_LIMIT_MSEC, data); | |
710 | g_variant_unref(data); | |
711 | if (ret != SR_OK) | |
712 | return ret; | |
713 | ||
714 | sr_sw_limits_acquisition_start(&devc->acq_limits); | |
715 | return SR_OK; | |
9a0a606a GS |
716 | } |
717 | ||
5e78a564 GS |
718 | /* |
719 | * Check whether a caller specified samplerate matches the device's | |
720 | * hardware constraints (can be used for acquisition). Optionally yield | |
721 | * a value that approximates the original spec. | |
722 | * | |
723 | * This routine assumes that input specs are in the 200kHz to 200MHz | |
724 | * range of supported rates, and callers typically want to normalize a | |
725 | * given value to the hardware capabilities. Values in the 50MHz range | |
726 | * get rounded up by default, to avoid a more expensive check for the | |
727 | * closest match, while higher sampling rate is always desirable during | |
728 | * measurement. Input specs which exactly match hardware capabilities | |
729 | * remain unaffected. Because 100/200MHz rates also limit the number of | |
730 | * available channels, they are not suggested by this routine, instead | |
731 | * callers need to pick them consciously. | |
732 | */ | |
733 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate) | |
734 | { | |
735 | uint64_t div, rate; | |
736 | ||
737 | /* Accept exact matches for 100/200MHz. */ | |
738 | if (want_rate == SR_MHZ(200) || want_rate == SR_MHZ(100)) { | |
739 | if (have_rate) | |
740 | *have_rate = want_rate; | |
741 | return SR_OK; | |
742 | } | |
743 | ||
744 | /* Accept 200kHz to 50MHz range, and map to near value. */ | |
745 | if (want_rate >= SR_KHZ(200) && want_rate <= SR_MHZ(50)) { | |
746 | div = SR_MHZ(50) / want_rate; | |
747 | rate = SR_MHZ(50) / div; | |
748 | if (have_rate) | |
749 | *have_rate = rate; | |
750 | return SR_OK; | |
751 | } | |
752 | ||
753 | return SR_ERR_ARG; | |
754 | } | |
755 | ||
756 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) | |
f6564c8d | 757 | { |
2c9c0df8 | 758 | struct dev_context *devc; |
8e2d6c9d | 759 | struct drv_context *drvc; |
5e78a564 | 760 | uint64_t samplerate; |
2c9c0df8 | 761 | int ret; |
ac9534f4 | 762 | int num_channels; |
f6564c8d | 763 | |
2c9c0df8 | 764 | devc = sdi->priv; |
8e2d6c9d | 765 | drvc = sdi->driver->context; |
f4abaa9f | 766 | |
5e78a564 GS |
767 | /* Accept any caller specified rate which the hardware supports. */ |
768 | ret = sigma_normalize_samplerate(devc->samplerate, &samplerate); | |
769 | if (ret != SR_OK) | |
770 | return ret; | |
f6564c8d | 771 | |
2f7e529c GS |
772 | /* |
773 | * Depending on the samplerates of 200/100/50- MHz, specific | |
774 | * firmware is required and higher rates might limit the set | |
775 | * of available channels. | |
776 | */ | |
ac9534f4 | 777 | num_channels = devc->num_channels; |
59df0c77 | 778 | if (samplerate <= SR_MHZ(50)) { |
80e717b3 | 779 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_50MHZ); |
ac9534f4 | 780 | num_channels = 16; |
6b2d3385 | 781 | } else if (samplerate == SR_MHZ(100)) { |
80e717b3 | 782 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_100MHZ); |
ac9534f4 | 783 | num_channels = 8; |
6b2d3385 | 784 | } else if (samplerate == SR_MHZ(200)) { |
80e717b3 | 785 | ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_200MHZ); |
ac9534f4 | 786 | num_channels = 4; |
f78898e9 | 787 | } |
f6564c8d | 788 | |
2f7e529c | 789 | /* |
5e78a564 GS |
790 | * The samplerate affects the number of available logic channels |
791 | * as well as a sample memory layout detail (the number of samples | |
792 | * which the device will communicate within an "event"). | |
2f7e529c | 793 | */ |
6b2d3385 | 794 | if (ret == SR_OK) { |
ac9534f4 | 795 | devc->num_channels = num_channels; |
6b2d3385 | 796 | devc->samples_per_event = 16 / devc->num_channels; |
6b2d3385 | 797 | } |
f6564c8d | 798 | |
e8397563 | 799 | return ret; |
28a35d8a HE |
800 | } |
801 | ||
98b43eb3 GS |
802 | /* |
803 | * Arrange for a session feed submit buffer. A queue where a number of | |
804 | * samples gets accumulated to reduce the number of send calls. Which | |
805 | * also enforces an optional sample count limit for data acquisition. | |
806 | * | |
807 | * The buffer holds up to CHUNK_SIZE bytes. The unit size is fixed (the | |
808 | * driver provides a fixed channel layout regardless of samplerate). | |
809 | */ | |
810 | ||
811 | #define CHUNK_SIZE (4 * 1024 * 1024) | |
812 | ||
813 | struct submit_buffer { | |
814 | size_t unit_size; | |
815 | size_t max_samples, curr_samples; | |
816 | uint8_t *sample_data; | |
817 | uint8_t *write_pointer; | |
818 | struct sr_dev_inst *sdi; | |
819 | struct sr_datafeed_packet packet; | |
820 | struct sr_datafeed_logic logic; | |
98b43eb3 GS |
821 | }; |
822 | ||
823 | static int alloc_submit_buffer(struct sr_dev_inst *sdi) | |
824 | { | |
825 | struct dev_context *devc; | |
826 | struct submit_buffer *buffer; | |
827 | size_t size; | |
828 | ||
829 | devc = sdi->priv; | |
830 | ||
831 | buffer = g_malloc0(sizeof(*buffer)); | |
832 | devc->buffer = buffer; | |
833 | ||
834 | buffer->unit_size = sizeof(uint16_t); | |
835 | size = CHUNK_SIZE; | |
836 | size /= buffer->unit_size; | |
837 | buffer->max_samples = size; | |
838 | size *= buffer->unit_size; | |
839 | buffer->sample_data = g_try_malloc0(size); | |
840 | if (!buffer->sample_data) | |
841 | return SR_ERR_MALLOC; | |
842 | buffer->write_pointer = buffer->sample_data; | |
5e78a564 | 843 | sr_sw_limits_init(&devc->feed_limits); |
98b43eb3 GS |
844 | |
845 | buffer->sdi = sdi; | |
846 | memset(&buffer->logic, 0, sizeof(buffer->logic)); | |
847 | buffer->logic.unitsize = buffer->unit_size; | |
848 | buffer->logic.data = buffer->sample_data; | |
849 | memset(&buffer->packet, 0, sizeof(buffer->packet)); | |
850 | buffer->packet.type = SR_DF_LOGIC; | |
851 | buffer->packet.payload = &buffer->logic; | |
852 | ||
853 | return SR_OK; | |
854 | } | |
855 | ||
5e78a564 | 856 | static int setup_submit_limit(struct dev_context *devc) |
98b43eb3 | 857 | { |
5e78a564 | 858 | struct sr_sw_limits *limits; |
98b43eb3 GS |
859 | int ret; |
860 | GVariant *data; | |
861 | uint64_t total; | |
862 | ||
5e78a564 | 863 | limits = &devc->feed_limits; |
98b43eb3 | 864 | |
5e78a564 GS |
865 | ret = sr_sw_limits_config_get(&devc->cfg_limits, |
866 | SR_CONF_LIMIT_SAMPLES, &data); | |
867 | if (ret != SR_OK) | |
868 | return ret; | |
869 | total = g_variant_get_uint64(data); | |
870 | g_variant_unref(data); | |
871 | ||
872 | sr_sw_limits_init(limits); | |
98b43eb3 GS |
873 | if (total) { |
874 | data = g_variant_new_uint64(total); | |
5e78a564 | 875 | ret = sr_sw_limits_config_set(limits, |
98b43eb3 GS |
876 | SR_CONF_LIMIT_SAMPLES, data); |
877 | g_variant_unref(data); | |
878 | if (ret != SR_OK) | |
879 | return ret; | |
880 | } | |
881 | ||
5e78a564 | 882 | sr_sw_limits_acquisition_start(limits); |
98b43eb3 GS |
883 | |
884 | return SR_OK; | |
885 | } | |
886 | ||
887 | static void free_submit_buffer(struct dev_context *devc) | |
888 | { | |
889 | struct submit_buffer *buffer; | |
890 | ||
891 | if (!devc) | |
892 | return; | |
893 | ||
894 | buffer = devc->buffer; | |
895 | if (!buffer) | |
896 | return; | |
897 | devc->buffer = NULL; | |
898 | ||
899 | g_free(buffer->sample_data); | |
900 | g_free(buffer); | |
901 | } | |
902 | ||
903 | static int flush_submit_buffer(struct dev_context *devc) | |
904 | { | |
905 | struct submit_buffer *buffer; | |
906 | int ret; | |
907 | ||
908 | buffer = devc->buffer; | |
909 | ||
910 | /* Is queued sample data available? */ | |
911 | if (!buffer->curr_samples) | |
912 | return SR_OK; | |
913 | ||
914 | /* Submit to the session feed. */ | |
915 | buffer->logic.length = buffer->curr_samples * buffer->unit_size; | |
916 | ret = sr_session_send(buffer->sdi, &buffer->packet); | |
917 | if (ret != SR_OK) | |
918 | return ret; | |
919 | ||
920 | /* Rewind queue position. */ | |
921 | buffer->curr_samples = 0; | |
922 | buffer->write_pointer = buffer->sample_data; | |
923 | ||
924 | return SR_OK; | |
925 | } | |
926 | ||
927 | static int addto_submit_buffer(struct dev_context *devc, | |
928 | uint16_t sample, size_t count) | |
929 | { | |
930 | struct submit_buffer *buffer; | |
5e78a564 | 931 | struct sr_sw_limits *limits; |
98b43eb3 GS |
932 | int ret; |
933 | ||
934 | buffer = devc->buffer; | |
5e78a564 GS |
935 | limits = &devc->feed_limits; |
936 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
937 | count = 0; |
938 | ||
939 | /* | |
940 | * Individually accumulate and check each sample, such that | |
941 | * accumulation between flushes won't exceed local storage, and | |
942 | * enforcement of user specified limits is exact. | |
943 | */ | |
944 | while (count--) { | |
a53b8e4d | 945 | write_u16le_inc(&buffer->write_pointer, sample); |
98b43eb3 GS |
946 | buffer->curr_samples++; |
947 | if (buffer->curr_samples == buffer->max_samples) { | |
948 | ret = flush_submit_buffer(devc); | |
949 | if (ret != SR_OK) | |
950 | return ret; | |
951 | } | |
5e78a564 GS |
952 | sr_sw_limits_update_samples_read(limits, 1); |
953 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
954 | break; |
955 | } | |
956 | ||
957 | return SR_OK; | |
958 | } | |
959 | ||
c53d793f HE |
960 | /* |
961 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
962 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 963 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
964 | * |
965 | * The Sigma supports complex triggers using boolean expressions, but this | |
966 | * has not been implemented yet. | |
967 | */ | |
3ba56876 | 968 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 969 | { |
39c64c6a BV |
970 | struct dev_context *devc; |
971 | struct sr_trigger *trigger; | |
972 | struct sr_trigger_stage *stage; | |
973 | struct sr_trigger_match *match; | |
974 | const GSList *l, *m; | |
975 | int channelbit, trigger_set; | |
57bbf56b | 976 | |
39c64c6a | 977 | devc = sdi->priv; |
0e1357e8 | 978 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 979 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
980 | return SR_OK; |
981 | ||
982 | trigger_set = 0; | |
983 | for (l = trigger->stages; l; l = l->next) { | |
984 | stage = l->data; | |
985 | for (m = stage->matches; m; m = m->next) { | |
986 | match = m->data; | |
9b4d261f | 987 | /* Ignore disabled channels with a trigger. */ |
39c64c6a | 988 | if (!match->channel->enabled) |
39c64c6a | 989 | continue; |
a53b8e4d | 990 | channelbit = 1 << match->channel->index; |
5e78a564 | 991 | if (devc->samplerate >= SR_MHZ(100)) { |
39c64c6a BV |
992 | /* Fast trigger support. */ |
993 | if (trigger_set) { | |
994 | sr_err("Only a single pin trigger is " | |
9b4d261f | 995 | "supported in 100 and 200MHz mode."); |
39c64c6a BV |
996 | return SR_ERR; |
997 | } | |
a53b8e4d | 998 | if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 999 | devc->trigger.fallingmask |= channelbit; |
a53b8e4d | 1000 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 1001 | devc->trigger.risingmask |= channelbit; |
a53b8e4d | 1002 | } else { |
39c64c6a | 1003 | sr_err("Only rising/falling trigger is " |
9b4d261f | 1004 | "supported in 100 and 200MHz mode."); |
39c64c6a BV |
1005 | return SR_ERR; |
1006 | } | |
eec5275e | 1007 | |
0a1f7b09 | 1008 | trigger_set++; |
39c64c6a BV |
1009 | } else { |
1010 | /* Simple trigger support (event). */ | |
1011 | if (match->match == SR_TRIGGER_ONE) { | |
1012 | devc->trigger.simplevalue |= channelbit; | |
1013 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 1014 | } else if (match->match == SR_TRIGGER_ZERO) { |
39c64c6a BV |
1015 | devc->trigger.simplevalue &= ~channelbit; |
1016 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 1017 | } else if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 1018 | devc->trigger.fallingmask |= channelbit; |
0a1f7b09 | 1019 | trigger_set++; |
8ebad343 | 1020 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 1021 | devc->trigger.risingmask |= channelbit; |
0a1f7b09 | 1022 | trigger_set++; |
39c64c6a BV |
1023 | } |
1024 | ||
1025 | /* | |
1026 | * Actually, Sigma supports 2 rising/falling triggers, | |
1027 | * but they are ORed and the current trigger syntax | |
1028 | * does not permit ORed triggers. | |
1029 | */ | |
1030 | if (trigger_set > 1) { | |
9b4d261f | 1031 | sr_err("Only 1 rising/falling trigger is supported."); |
39c64c6a BV |
1032 | return SR_ERR; |
1033 | } | |
ee492173 | 1034 | } |
ee492173 | 1035 | } |
57bbf56b HE |
1036 | } |
1037 | ||
e46b8fb1 | 1038 | return SR_OK; |
57bbf56b HE |
1039 | } |
1040 | ||
36b1c8e6 | 1041 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 1042 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
9b4d261f | 1043 | struct sigma_trigger *t) |
36b1c8e6 | 1044 | { |
a53b8e4d | 1045 | const uint8_t *rdptr; |
36b1c8e6 | 1046 | int i; |
a53b8e4d | 1047 | uint16_t sample; |
36b1c8e6 | 1048 | |
a53b8e4d GS |
1049 | rdptr = samples; |
1050 | sample = 0; | |
0a1f7b09 | 1051 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 1052 | if (i > 0) |
5fc01191 | 1053 | last_sample = sample; |
a53b8e4d | 1054 | sample = read_u16le_inc(&rdptr); |
36b1c8e6 HE |
1055 | |
1056 | /* Simple triggers. */ | |
5fc01191 | 1057 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
1058 | continue; |
1059 | ||
1060 | /* Rising edge. */ | |
5fc01191 MV |
1061 | if (((last_sample & t->risingmask) != 0) || |
1062 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
1063 | continue; |
1064 | ||
1065 | /* Falling edge. */ | |
bdfc7a89 | 1066 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 1067 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
1068 | continue; |
1069 | ||
1070 | break; | |
1071 | } | |
1072 | ||
1073 | /* If we did not match, return original trigger pos. */ | |
1074 | return i & 0x7; | |
1075 | } | |
1076 | ||
98b43eb3 GS |
1077 | static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample) |
1078 | { | |
1079 | /* TODO | |
1080 | * Check whether the combination of this very sample and the | |
1081 | * previous state match the configured trigger condition. This | |
1082 | * improves the resolution of the trigger marker's position. | |
1083 | * The hardware provided position is coarse, and may point to | |
1084 | * a position before the actual match. | |
1085 | * | |
1086 | * See the previous get_trigger_offset() implementation. This | |
1087 | * code needs to get re-used here. | |
1088 | */ | |
1089 | (void)devc; | |
1090 | (void)sample; | |
1091 | (void)get_trigger_offset; | |
1092 | ||
1093 | return FALSE; | |
1094 | } | |
1095 | ||
1096 | static int check_and_submit_sample(struct dev_context *devc, | |
1097 | uint16_t sample, size_t count, gboolean check_trigger) | |
1098 | { | |
1099 | gboolean triggered; | |
1100 | int ret; | |
1101 | ||
1102 | triggered = check_trigger && sample_matches_trigger(devc, sample); | |
1103 | if (triggered) { | |
1104 | ret = flush_submit_buffer(devc); | |
1105 | if (ret != SR_OK) | |
1106 | return ret; | |
1107 | ret = std_session_send_df_trigger(devc->buffer->sdi); | |
1108 | if (ret != SR_OK) | |
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | ret = addto_submit_buffer(devc, sample, count); | |
1113 | if (ret != SR_OK) | |
1114 | return ret; | |
1115 | ||
1116 | return SR_OK; | |
1117 | } | |
1118 | ||
3513d965 MV |
1119 | /* |
1120 | * Return the timestamp of "DRAM cluster". | |
1121 | */ | |
1122 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
1123 | { | |
a53b8e4d | 1124 | return read_u16le(&cluster->timestamp[0]); |
3513d965 MV |
1125 | } |
1126 | ||
0498f743 GS |
1127 | /* |
1128 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
1129 | */ | |
1130 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
1131 | { | |
a53b8e4d | 1132 | return read_u16le(&cl->samples[idx].sample[0]); |
0498f743 GS |
1133 | } |
1134 | ||
85c032e4 GS |
1135 | /* |
1136 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
1137 | * One 16bit item contains two samples of 8bits each. The bits of | |
1138 | * multiple samples are interleaved. | |
1139 | */ | |
1140 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
1141 | { | |
1142 | uint16_t outdata; | |
1143 | ||
1144 | indata >>= idx; | |
1145 | outdata = 0; | |
1146 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
1147 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
1148 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
1149 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
1150 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
1151 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
1152 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
1153 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
1154 | return outdata; | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
1159 | * One 16bit item contains four samples of 4bits each. The bits of | |
1160 | * multiple samples are interleaved. | |
1161 | */ | |
1162 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
1163 | { | |
1164 | uint16_t outdata; | |
1165 | ||
1166 | indata >>= idx; | |
1167 | outdata = 0; | |
1168 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
1169 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
1170 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
1171 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
1172 | return outdata; | |
1173 | } | |
1174 | ||
98b43eb3 GS |
1175 | static void sigma_decode_dram_cluster(struct dev_context *devc, |
1176 | struct sigma_dram_cluster *dram_cluster, | |
1177 | size_t events_in_cluster, gboolean triggered) | |
23239b5c | 1178 | { |
98b43eb3 | 1179 | struct sigma_state *ss; |
85c032e4 | 1180 | uint16_t tsdiff, ts, sample, item16; |
23239b5c | 1181 | unsigned int i; |
23239b5c | 1182 | |
98b43eb3 GS |
1183 | if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER) |
1184 | triggered = FALSE; | |
23239b5c MV |
1185 | |
1186 | /* | |
468f17f2 GS |
1187 | * If this cluster is not adjacent to the previously received |
1188 | * cluster, then send the appropriate number of samples with the | |
1189 | * previous values to the sigrok session. This "decodes RLE". | |
2c33b092 | 1190 | * |
98b43eb3 GS |
1191 | * These samples cannot match the trigger since they just repeat |
1192 | * the previously submitted data pattern. (This assumption holds | |
1193 | * for simple level and edge triggers. It would not for timed or | |
1194 | * counted conditions, which currently are not supported.) | |
23239b5c | 1195 | */ |
98b43eb3 GS |
1196 | ss = &devc->state; |
1197 | ts = sigma_dram_cluster_ts(dram_cluster); | |
1198 | tsdiff = ts - ss->lastts; | |
1199 | if (tsdiff > 0) { | |
1200 | size_t count; | |
9b4d261f | 1201 | sample = ss->lastsample; |
98b43eb3 | 1202 | count = tsdiff * devc->samples_per_event; |
9b4d261f | 1203 | (void)check_and_submit_sample(devc, sample, count, FALSE); |
23239b5c | 1204 | } |
98b43eb3 | 1205 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
1206 | |
1207 | /* | |
98b43eb3 GS |
1208 | * Grab sample data from the current cluster and prepare their |
1209 | * submission to the session feed. Handle samplerate dependent | |
1210 | * memory layout of sample data. Accumulation of data chunks | |
1211 | * before submission is transparent to this code path, specific | |
1212 | * buffer depth is neither assumed nor required here. | |
23239b5c | 1213 | */ |
0498f743 | 1214 | sample = 0; |
23239b5c | 1215 | for (i = 0; i < events_in_cluster; i++) { |
85c032e4 | 1216 | item16 = sigma_dram_cluster_data(dram_cluster, i); |
5e78a564 | 1217 | if (devc->samplerate == SR_MHZ(200)) { |
85c032e4 | 1218 | sample = sigma_deinterlace_200mhz_data(item16, 0); |
98b43eb3 | 1219 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1220 | sample = sigma_deinterlace_200mhz_data(item16, 1); |
98b43eb3 | 1221 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1222 | sample = sigma_deinterlace_200mhz_data(item16, 2); |
98b43eb3 | 1223 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1224 | sample = sigma_deinterlace_200mhz_data(item16, 3); |
98b43eb3 | 1225 | check_and_submit_sample(devc, sample, 1, triggered); |
5e78a564 | 1226 | } else if (devc->samplerate == SR_MHZ(100)) { |
85c032e4 | 1227 | sample = sigma_deinterlace_100mhz_data(item16, 0); |
98b43eb3 | 1228 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1229 | sample = sigma_deinterlace_100mhz_data(item16, 1); |
98b43eb3 | 1230 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 GS |
1231 | } else { |
1232 | sample = item16; | |
98b43eb3 | 1233 | check_and_submit_sample(devc, sample, 1, triggered); |
23239b5c | 1234 | } |
23239b5c | 1235 | } |
0498f743 | 1236 | ss->lastsample = sample; |
23239b5c MV |
1237 | } |
1238 | ||
28a35d8a | 1239 | /* |
fefa1800 UH |
1240 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
1241 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
1242 | * |
1243 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
1244 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
1245 | * For 50 MHz and below, events contain one sample for each channel, | |
1246 | * spread 20 ns apart. | |
28a35d8a | 1247 | */ |
98b43eb3 GS |
1248 | static int decode_chunk_ts(struct dev_context *devc, |
1249 | struct sigma_dram_line *dram_line, | |
1250 | size_t events_in_line, size_t trigger_event) | |
28a35d8a | 1251 | { |
3628074d | 1252 | struct sigma_dram_cluster *dram_cluster; |
f06fb3e9 | 1253 | unsigned int clusters_in_line; |
5fc01191 | 1254 | unsigned int events_in_cluster; |
23239b5c | 1255 | unsigned int i; |
98b43eb3 | 1256 | uint32_t trigger_cluster; |
f06fb3e9 | 1257 | |
f06fb3e9 GS |
1258 | clusters_in_line = events_in_line; |
1259 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
1260 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
1261 | trigger_cluster = ~0; | |
ee492173 | 1262 | |
4ae1f451 | 1263 | /* Check if trigger is in this chunk. */ |
2c33b092 | 1264 | if (trigger_event < EVENTS_PER_ROW) { |
5e78a564 | 1265 | if (devc->samplerate <= SR_MHZ(50)) { |
1e23158b MV |
1266 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, |
1267 | trigger_event); | |
1268 | } | |
57bbf56b | 1269 | |
f3f19d11 | 1270 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 1271 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1272 | } |
28a35d8a | 1273 | |
5fc01191 MV |
1274 | /* For each full DRAM cluster. */ |
1275 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 1276 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 1277 | |
5fc01191 | 1278 | /* The last cluster might not be full. */ |
23239b5c MV |
1279 | if ((i == clusters_in_line - 1) && |
1280 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 1281 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1282 | } else { |
5fc01191 | 1283 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1284 | } |
ee492173 | 1285 | |
98b43eb3 GS |
1286 | sigma_decode_dram_cluster(devc, dram_cluster, |
1287 | events_in_cluster, i == trigger_cluster); | |
28a35d8a HE |
1288 | } |
1289 | ||
e46b8fb1 | 1290 | return SR_OK; |
28a35d8a HE |
1291 | } |
1292 | ||
6057d9fa | 1293 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1294 | { |
e15e5873 | 1295 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
1296 | |
1297 | struct dev_context *devc; | |
fd830beb | 1298 | struct sigma_dram_line *dram_line; |
c6648b66 | 1299 | int bufsz; |
462fe786 | 1300 | uint32_t stoppos, triggerpos; |
6057d9fa | 1301 | uint8_t modestatus; |
c6648b66 MV |
1302 | uint32_t i; |
1303 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
74d453ab | 1304 | uint32_t dl_first_line, dl_line; |
f06fb3e9 GS |
1305 | uint32_t dl_events_in_line; |
1306 | uint32_t trg_line, trg_event; | |
98b43eb3 | 1307 | int ret; |
f06fb3e9 GS |
1308 | |
1309 | devc = sdi->priv; | |
2c33b092 | 1310 | dl_events_in_line = EVENTS_PER_ROW; |
c6648b66 | 1311 | |
6868626b | 1312 | sr_info("Downloading sample data."); |
dde0175d | 1313 | devc->state.state = SIGMA_DOWNLOAD; |
6868626b | 1314 | |
22f64ed8 GS |
1315 | /* |
1316 | * Ask the hardware to stop data acquisition. Reception of the | |
1317 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1318 | * clusters to DRAM regardless of whether pin state changes) and | |
1319 | * raise the POSTTRIGGERED flag. | |
1320 | */ | |
9b4d261f | 1321 | sigma_set_register(devc, WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN); |
22f64ed8 | 1322 | do { |
a53b8e4d GS |
1323 | ret = sigma_read_register(devc, READ_MODE, |
1324 | &modestatus, sizeof(modestatus)); | |
1325 | if (ret != sizeof(modestatus)) { | |
1326 | sr_err("Could not poll for post-trigger condition."); | |
f73b00b6 DT |
1327 | return FALSE; |
1328 | } | |
22f64ed8 | 1329 | } while (!(modestatus & RMR_POSTTRIGGERED)); |
6057d9fa MV |
1330 | |
1331 | /* Set SDRAM Read Enable. */ | |
9b4d261f | 1332 | sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN); |
6057d9fa MV |
1333 | |
1334 | /* Get the current position. */ | |
9b4d261f | 1335 | sigma_read_pos(devc, &stoppos, &triggerpos); |
6057d9fa MV |
1336 | |
1337 | /* Check if trigger has fired. */ | |
a53b8e4d GS |
1338 | ret = sigma_read_register(devc, READ_MODE, |
1339 | &modestatus, sizeof(modestatus)); | |
1340 | if (ret != sizeof(modestatus)) { | |
1341 | sr_err("Could not query trigger hit."); | |
f73b00b6 DT |
1342 | return FALSE; |
1343 | } | |
dc400817 GS |
1344 | trg_line = ~0; |
1345 | trg_event = ~0; | |
22f64ed8 | 1346 | if (modestatus & RMR_TRIGGERED) { |
a53b8e4d GS |
1347 | trg_line = triggerpos >> ROW_SHIFT; |
1348 | trg_event = triggerpos & ROW_MASK; | |
1e23158b | 1349 | } |
6057d9fa | 1350 | |
c6648b66 | 1351 | /* |
74d453ab GS |
1352 | * Determine how many "DRAM lines" of 1024 bytes each we need to |
1353 | * retrieve from the Sigma hardware, so that we have a complete | |
1354 | * set of samples. Note that the last line need not contain 64 | |
1355 | * clusters, it might be partially filled only. | |
1356 | * | |
1357 | * When RMR_ROUND is set, the circular buffer in DRAM has wrapped | |
1358 | * around. Since the status of the very next line is uncertain in | |
2c33b092 | 1359 | * that case, we skip it and start reading from the next line. |
c6648b66 | 1360 | */ |
2c33b092 GS |
1361 | dl_first_line = 0; |
1362 | dl_lines_total = (stoppos >> ROW_SHIFT) + 1; | |
74d453ab GS |
1363 | if (modestatus & RMR_ROUND) { |
1364 | dl_first_line = dl_lines_total + 1; | |
2c33b092 | 1365 | dl_lines_total = ROW_COUNT - 2; |
74d453ab | 1366 | } |
44081095 DT |
1367 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1368 | if (!dram_line) | |
1369 | return FALSE; | |
98b43eb3 GS |
1370 | ret = alloc_submit_buffer(sdi); |
1371 | if (ret != SR_OK) | |
1372 | return FALSE; | |
5e78a564 | 1373 | ret = setup_submit_limit(devc); |
98b43eb3 GS |
1374 | if (ret != SR_OK) |
1375 | return FALSE; | |
c6648b66 | 1376 | dl_lines_done = 0; |
c6648b66 MV |
1377 | while (dl_lines_total > dl_lines_done) { |
1378 | /* We can download only up-to 32 DRAM lines in one go! */ | |
547c4cdc | 1379 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); |
6868626b | 1380 | |
74d453ab | 1381 | dl_line = dl_first_line + dl_lines_done; |
2c33b092 | 1382 | dl_line %= ROW_COUNT; |
9b4d261f GS |
1383 | bufsz = sigma_read_dram(devc, dl_line, dl_lines_curr, |
1384 | (uint8_t *)dram_line); | |
c6648b66 MV |
1385 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1386 | (void)bufsz; | |
6868626b | 1387 | |
c6648b66 MV |
1388 | /* This is the first DRAM line, so find the initial timestamp. */ |
1389 | if (dl_lines_done == 0) { | |
3513d965 MV |
1390 | devc->state.lastts = |
1391 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1392 | devc->state.lastsample = 0; |
6868626b BV |
1393 | } |
1394 | ||
c6648b66 | 1395 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1396 | uint32_t trigger_event = ~0; |
a53b8e4d | 1397 | /* The last "DRAM line" need not span its full length. */ |
c6648b66 | 1398 | if (dl_lines_done + i == dl_lines_total - 1) |
a53b8e4d | 1399 | dl_events_in_line = stoppos & ROW_MASK; |
c6648b66 | 1400 | |
e69ad48e | 1401 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1402 | if (dl_lines_done + i == trg_line) |
1e23158b | 1403 | trigger_event = trg_event; |
e69ad48e | 1404 | |
98b43eb3 GS |
1405 | decode_chunk_ts(devc, dram_line + i, |
1406 | dl_events_in_line, trigger_event); | |
c6648b66 | 1407 | } |
6868626b | 1408 | |
c6648b66 | 1409 | dl_lines_done += dl_lines_curr; |
6868626b | 1410 | } |
98b43eb3 GS |
1411 | flush_submit_buffer(devc); |
1412 | free_submit_buffer(devc); | |
dde0175d | 1413 | g_free(dram_line); |
6868626b | 1414 | |
bee2b016 | 1415 | std_session_send_df_end(sdi); |
6057d9fa | 1416 | |
dde0175d | 1417 | devc->state.state = SIGMA_IDLE; |
d2f7c417 | 1418 | sr_dev_acquisition_stop(sdi); |
6057d9fa MV |
1419 | |
1420 | return TRUE; | |
6868626b BV |
1421 | } |
1422 | ||
d4051930 | 1423 | /* |
74d453ab GS |
1424 | * Periodically check the Sigma status when in CAPTURE mode. This routine |
1425 | * checks whether the configured sample count or sample time have passed, | |
1426 | * and will stop acquisition and download the acquired samples. | |
d4051930 MV |
1427 | */ |
1428 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1429 | { |
f06fb3e9 | 1430 | struct dev_context *devc; |
28a35d8a | 1431 | |
f06fb3e9 | 1432 | devc = sdi->priv; |
5e78a564 | 1433 | if (sr_sw_limits_check(&devc->acq_limits)) |
6057d9fa | 1434 | return download_capture(sdi); |
00c86508 | 1435 | |
d4051930 MV |
1436 | return TRUE; |
1437 | } | |
28a35d8a | 1438 | |
3ba56876 | 1439 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1440 | { |
1441 | struct sr_dev_inst *sdi; | |
1442 | struct dev_context *devc; | |
88c51afe | 1443 | |
d4051930 MV |
1444 | (void)fd; |
1445 | (void)revents; | |
88c51afe | 1446 | |
d4051930 MV |
1447 | sdi = cb_data; |
1448 | devc = sdi->priv; | |
1449 | ||
1450 | if (devc->state.state == SIGMA_IDLE) | |
1451 | return TRUE; | |
1452 | ||
dde0175d GS |
1453 | /* |
1454 | * When the application has requested to stop the acquisition, | |
1455 | * then immediately start downloading sample data. Otherwise | |
1456 | * keep checking configured limits which will terminate the | |
1457 | * acquisition and initiate download. | |
1458 | */ | |
1459 | if (devc->state.state == SIGMA_STOPPING) | |
1460 | return download_capture(sdi); | |
d4051930 MV |
1461 | if (devc->state.state == SIGMA_CAPTURE) |
1462 | return sigma_capture_mode(sdi); | |
28a35d8a | 1463 | |
28a35d8a HE |
1464 | return TRUE; |
1465 | } | |
1466 | ||
c53d793f HE |
1467 | /* Build a LUT entry used by the trigger functions. */ |
1468 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1469 | { |
1470 | int i, j, k, bit; | |
1471 | ||
ba7dd8bb | 1472 | /* For each quad channel. */ |
0a1f7b09 | 1473 | for (i = 0; i < 4; i++) { |
c53d793f | 1474 | entry[i] = 0xffff; |
ee492173 | 1475 | |
f758d074 | 1476 | /* For each bit in LUT. */ |
a53b8e4d | 1477 | for (j = 0; j < 16; j++) { |
ee492173 | 1478 | |
ba7dd8bb | 1479 | /* For each channel in quad. */ |
0a1f7b09 | 1480 | for (k = 0; k < 4; k++) { |
ee492173 HE |
1481 | bit = 1 << (i * 4 + k); |
1482 | ||
c53d793f | 1483 | /* Set bit in entry */ |
0a1f7b09 UH |
1484 | if ((mask & bit) && ((!(value & bit)) != |
1485 | (!(j & (1 << k))))) | |
c53d793f | 1486 | entry[i] &= ~(1 << j); |
ee492173 | 1487 | } |
a53b8e4d | 1488 | } |
ee492173 | 1489 | } |
c53d793f | 1490 | } |
ee492173 | 1491 | |
c53d793f HE |
1492 | /* Add a logical function to LUT mask. */ |
1493 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
9b4d261f | 1494 | int index, int neg, uint16_t *mask) |
c53d793f HE |
1495 | { |
1496 | int i, j; | |
1497 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1498 | ||
1499 | memset(x, 0, 4 * sizeof(int)); | |
1500 | ||
1501 | /* Trigger detect condition. */ | |
1502 | switch (oper) { | |
1503 | case OP_LEVEL: | |
1504 | x[0][1] = 1; | |
1505 | x[1][1] = 1; | |
1506 | break; | |
1507 | case OP_NOT: | |
1508 | x[0][0] = 1; | |
1509 | x[1][0] = 1; | |
1510 | break; | |
1511 | case OP_RISE: | |
1512 | x[0][1] = 1; | |
1513 | break; | |
1514 | case OP_FALL: | |
1515 | x[1][0] = 1; | |
1516 | break; | |
1517 | case OP_RISEFALL: | |
1518 | x[0][1] = 1; | |
1519 | x[1][0] = 1; | |
1520 | break; | |
1521 | case OP_NOTRISE: | |
1522 | x[1][1] = 1; | |
1523 | x[0][0] = 1; | |
1524 | x[1][0] = 1; | |
1525 | break; | |
1526 | case OP_NOTFALL: | |
1527 | x[1][1] = 1; | |
1528 | x[0][0] = 1; | |
1529 | x[0][1] = 1; | |
1530 | break; | |
1531 | case OP_NOTRISEFALL: | |
1532 | x[1][1] = 1; | |
1533 | x[0][0] = 1; | |
1534 | break; | |
1535 | } | |
1536 | ||
1537 | /* Transpose if neg is set. */ | |
1538 | if (neg) { | |
0a1f7b09 UH |
1539 | for (i = 0; i < 2; i++) { |
1540 | for (j = 0; j < 2; j++) { | |
c53d793f | 1541 | tmp = x[i][j]; |
0a1f7b09 UH |
1542 | x[i][j] = x[1 - i][1 - j]; |
1543 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1544 | } |
ea9cfed7 | 1545 | } |
c53d793f HE |
1546 | } |
1547 | ||
1548 | /* Update mask with function. */ | |
0a1f7b09 | 1549 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1550 | a = (i >> (2 * index + 0)) & 1; |
1551 | b = (i >> (2 * index + 1)) & 1; | |
1552 | ||
1553 | aset = (*mask >> i) & 1; | |
1554 | bset = x[b][a]; | |
1555 | ||
382cb19f | 1556 | rset = 0; |
c53d793f HE |
1557 | if (func == FUNC_AND || func == FUNC_NAND) |
1558 | rset = aset & bset; | |
1559 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1560 | rset = aset | bset; | |
1561 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1562 | rset = aset ^ bset; | |
1563 | ||
1564 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1565 | rset = !rset; | |
1566 | ||
1567 | *mask &= ~(1 << i); | |
1568 | ||
1569 | if (rset) | |
1570 | *mask |= 1 << i; | |
1571 | } | |
1572 | } | |
1573 | ||
1574 | /* | |
1575 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1576 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1577 | * set at any time, but a full mask and value can be set (0/1). | |
1578 | */ | |
9b4d261f GS |
1579 | SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, |
1580 | struct triggerlut *lut) | |
c53d793f HE |
1581 | { |
1582 | int i,j; | |
4ae1f451 | 1583 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1584 | |
1585 | memset(lut, 0, sizeof(struct triggerlut)); | |
1586 | ||
f3f19d11 | 1587 | /* Constant for simple triggers. */ |
c53d793f HE |
1588 | lut->m4 = 0xa000; |
1589 | ||
1590 | /* Value/mask trigger support. */ | |
0e1357e8 | 1591 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1592 | lut->m2d); |
c53d793f HE |
1593 | |
1594 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1595 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1596 | if (devc->trigger.risingmask & (1 << i) || |
1597 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1598 | masks[j++] = 1 << i; |
1599 | } | |
1600 | ||
1601 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1602 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1603 | ||
1604 | /* Add glue logic */ | |
1605 | if (masks[0] || masks[1]) { | |
1606 | /* Transition trigger. */ | |
0e1357e8 | 1607 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1608 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1609 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1610 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1611 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1612 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1613 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1614 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1615 | } else { | |
1616 | /* Only value/mask trigger. */ | |
1617 | lut->m3 = 0xffff; | |
1618 | } | |
ee492173 | 1619 | |
c53d793f | 1620 | /* Triggertype: event. */ |
ee492173 HE |
1621 | lut->params.selres = 3; |
1622 | ||
e46b8fb1 | 1623 | return SR_OK; |
ee492173 | 1624 | } |