]>
Commit | Line | Data |
---|---|---|
d5f5ea73 | 1 | /* |
a986cfff | 2 | * This file is part of the sigrok-firmware-fx2lafw project. |
d5f5ea73 UH |
3 | * |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
040a6eae | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
d5f5ea73 UH |
18 | */ |
19 | ||
20 | /* | |
21 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
22 | * | |
23 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
24 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
25 | * | |
26 | * Technical notes: | |
27 | * | |
28 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
29 | * - We use the internal 48MHz clock for GPIF. | |
c7e02d8c UH |
30 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7, |
31 | * or PB0-PB7 + PD0-PD7 for 16-channel sampling. | |
32 | * - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host. | |
d5f5ea73 UH |
33 | * |
34 | * Documentation: | |
35 | * | |
36 | * - See http://sigrok.org/wiki/Fx2lafw | |
37 | */ | |
38 | ||
39 | #include <fx2regs.h> | |
40 | #include <fx2macros.h> | |
cf43e09a | 41 | #include <fx2ints.h> |
d5f5ea73 | 42 | #include <delay.h> |
d5f5ea73 UH |
43 | #include <setupdat.h> |
44 | #include <eputils.h> | |
45 | #include <gpif.h> | |
64d47730 | 46 | #include <command.h> |
8f4a701f | 47 | #include <fx2lafw.h> |
e41576ec | 48 | #include <gpif-acquisition.h> |
d5f5ea73 | 49 | |
d5f5ea73 | 50 | /* ... */ |
8819f75c | 51 | volatile __bit got_sud; |
2846a114 | 52 | BYTE vendor_command; |
d5f5ea73 | 53 | |
cfeb1a36 | 54 | volatile WORD ledcounter = 0; |
cf43e09a | 55 | |
d5f5ea73 UH |
56 | static void setup_endpoints(void) |
57 | { | |
d5f5ea73 | 58 | /* Setup EP2 (IN). */ |
f6ef2ff7 GS |
59 | EP2CFG = (1u << 7) | /* EP is valid/activated */ |
60 | (1u << 6) | /* EP direction: IN */ | |
61 | (1u << 5) | (0u << 4) | /* EP Type: bulk */ | |
62 | (1u << 3) | /* EP buffer size: 1024 */ | |
63 | (0u << 2) | /* Reserved. */ | |
64 | (0u << 1) | (0u << 0); /* EP buffering: quad buffering */ | |
d5f5ea73 UH |
65 | SYNCDELAY(); |
66 | ||
576c6627 | 67 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ |
4ad20a4c UH |
68 | EP1INCFG &= ~bmVALID; |
69 | SYNCDELAY(); | |
70 | EP1OUTCFG &= ~bmVALID; | |
71 | SYNCDELAY(); | |
d5f5ea73 UH |
72 | EP4CFG &= ~bmVALID; |
73 | SYNCDELAY(); | |
576c6627 JH |
74 | EP6CFG &= ~bmVALID; |
75 | SYNCDELAY(); | |
d5f5ea73 UH |
76 | EP8CFG &= ~bmVALID; |
77 | SYNCDELAY(); | |
78 | ||
4ad20a4c | 79 | /* EP2: Reset the FIFOs. */ |
d5f5ea73 | 80 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ |
14d3dfb7 | 81 | RESETFIFO(0x02); |
2d62ae47 | 82 | |
dc7ac8bf | 83 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ |
2d62ae47 | 84 | EP2FIFOCFG = bmAUTOIN; |
dc7ac8bf UH |
85 | SYNCDELAY(); |
86 | ||
87 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
88 | EP2AUTOINLENH = 0x02; | |
89 | SYNCDELAY(); | |
90 | EP2AUTOINLENL = 0x00; | |
91 | SYNCDELAY(); | |
92 | ||
4ad20a4c | 93 | /* EP2: Set the GPIF flag to 'full'. */ |
fb0b6d28 | 94 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); |
d5f5ea73 UH |
95 | SYNCDELAY(); |
96 | } | |
97 | ||
18544912 JH |
98 | static void send_fw_version(void) |
99 | { | |
cd29817d UH |
100 | /* Populate the buffer. */ |
101 | struct version_info *const vi = (struct version_info *)EP0BUF; | |
18544912 JH |
102 | vi->major = FX2LAFW_VERSION_MAJOR; |
103 | vi->minor = FX2LAFW_VERSION_MINOR; | |
104 | ||
cd29817d | 105 | /* Send the message. */ |
18544912 | 106 | EP0BCH = 0; |
57b6b3a3 | 107 | SYNCDELAY(); |
18544912 | 108 | EP0BCL = sizeof(struct version_info); |
57b6b3a3 | 109 | SYNCDELAY(); |
18544912 JH |
110 | } |
111 | ||
c23ad602 UH |
112 | static void send_revid_version(void) |
113 | { | |
114 | uint8_t *p; | |
115 | ||
116 | /* Populate the buffer. */ | |
117 | p = (uint8_t *)EP0BUF; | |
118 | *p = REVID; | |
119 | ||
120 | /* Send the message. */ | |
121 | EP0BCH = 0; | |
57b6b3a3 | 122 | SYNCDELAY(); |
c23ad602 | 123 | EP0BCL = 1; |
57b6b3a3 | 124 | SYNCDELAY(); |
c23ad602 UH |
125 | } |
126 | ||
d5f5ea73 UH |
127 | BOOL handle_vendorcommand(BYTE cmd) |
128 | { | |
c7283c28 | 129 | /* Protocol implementation */ |
c7283c28 | 130 | switch (cmd) { |
3b6919fa | 131 | case CMD_START: |
cfeb1a36 | 132 | /* Tell hardware we are ready to receive data. */ |
18544912 | 133 | vendor_command = cmd; |
2846a114 | 134 | EP0BCL = 0; |
57b6b3a3 | 135 | SYNCDELAY(); |
18544912 | 136 | return TRUE; |
2846a114 | 137 | case CMD_GET_FW_VERSION: |
18544912 | 138 | send_fw_version(); |
3b6919fa | 139 | return TRUE; |
c23ad602 UH |
140 | case CMD_GET_REVID_VERSION: |
141 | send_revid_version(); | |
142 | return TRUE; | |
c7283c28 | 143 | } |
4ad20a4c | 144 | |
d5f5ea73 UH |
145 | return FALSE; |
146 | } | |
147 | ||
148 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
149 | { | |
150 | /* We only support interface 0, alternate interface 0. */ | |
151 | if (ifc != 0) | |
152 | return FALSE; | |
153 | ||
154 | *alt_ifc = 0; | |
155 | return TRUE; | |
156 | } | |
157 | ||
158 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
159 | { | |
160 | /* We only support interface 0, alternate interface 0. */ | |
161 | if (ifc != 0 || alt_ifc != 0) | |
162 | return FALSE; | |
c7e02d8c | 163 | |
d5f5ea73 UH |
164 | /* Perform procedure from TRM, section 2.3.7: */ |
165 | ||
166 | /* (1) TODO. */ | |
167 | ||
168 | /* (2) Reset data toggles of the EPs in the interface. */ | |
169 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
d5f5ea73 UH |
170 | RESETTOGGLE(0x82); |
171 | ||
172 | /* (3) Restore EPs to their default conditions. */ | |
173 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
d5f5ea73 UH |
174 | RESETFIFO(0x02); |
175 | /* TODO */ | |
c430e296 | 176 | |
d5f5ea73 UH |
177 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ |
178 | ||
179 | return TRUE; | |
180 | } | |
181 | ||
182 | BYTE handle_get_configuration(void) | |
183 | { | |
184 | /* We only support configuration 1. */ | |
185 | return 1; | |
186 | } | |
187 | ||
188 | BOOL handle_set_configuration(BYTE cfg) | |
189 | { | |
190 | /* We only support configuration 1. */ | |
191 | return (cfg == 1) ? TRUE : FALSE; | |
192 | } | |
193 | ||
8819f75c | 194 | void sudav_isr(void) __interrupt SUDAV_ISR |
d5f5ea73 UH |
195 | { |
196 | got_sud = TRUE; | |
197 | CLEAR_SUDAV(); | |
198 | } | |
199 | ||
cfeb1a36 SB |
200 | /* IN BULK NAK - the host started requesting data. */ |
201 | void ibn_isr(void) __interrupt IBN_ISR | |
202 | { | |
203 | /* | |
204 | * If the IBN interrupt is not disabled, clearing | |
205 | * does not work. See AN78446, 6.2. | |
206 | */ | |
207 | BYTE ibnsave = IBNIE; | |
208 | IBNIE = 0; | |
209 | CLEAR_USBINT(); | |
210 | ||
211 | /* | |
212 | * If the host sent the START command, start the GPIF | |
213 | * engine. The host will repeat the BULK IN in the next | |
214 | * microframe. | |
215 | */ | |
216 | if ((IBNIRQ & bmEP2IBN) && (gpif_acquiring == PREPARED)) { | |
217 | ledcounter = 1; | |
553c0ee3 | 218 | LED_OFF(); |
cfeb1a36 SB |
219 | gpif_acquisition_start(); |
220 | } | |
221 | ||
222 | /* Clear IBN flags for all EPs. */ | |
223 | IBNIRQ = 0xff; | |
224 | ||
225 | NAKIRQ = bmIBN; | |
226 | SYNCDELAY(); | |
227 | ||
228 | IBNIE = ibnsave; | |
229 | SYNCDELAY(); | |
230 | } | |
231 | ||
8819f75c | 232 | void usbreset_isr(void) __interrupt USBRESET_ISR |
d5f5ea73 UH |
233 | { |
234 | handle_hispeed(FALSE); | |
235 | CLEAR_USBRESET(); | |
236 | } | |
237 | ||
8819f75c | 238 | void hispeed_isr(void) __interrupt HISPEED_ISR |
d5f5ea73 UH |
239 | { |
240 | handle_hispeed(TRUE); | |
241 | CLEAR_HISPEED(); | |
242 | } | |
243 | ||
cf43e09a UH |
244 | void timer2_isr(void) __interrupt TF2_ISR |
245 | { | |
246 | /* Blink LED during acquisition, keep it on otherwise. */ | |
cfeb1a36 | 247 | if (gpif_acquiring == RUNNING) { |
cf43e09a | 248 | if (--ledcounter == 0) { |
553c0ee3 | 249 | LED_TOGGLE(); |
cf43e09a UH |
250 | ledcounter = 1000; |
251 | } | |
cfeb1a36 | 252 | } else if (gpif_acquiring == STOPPED) { |
553c0ee3 | 253 | LED_ON(); |
cf43e09a UH |
254 | } |
255 | TF2 = 0; | |
256 | } | |
257 | ||
1cbff47d | 258 | void fx2lafw_init(void) |
d5f5ea73 UH |
259 | { |
260 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
e7434142 | 261 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; |
d5f5ea73 UH |
262 | |
263 | got_sud = FALSE; | |
2846a114 | 264 | vendor_command = 0; |
d5f5ea73 UH |
265 | |
266 | /* Renumerate. */ | |
267 | RENUMERATE_UNCOND(); | |
268 | ||
269 | SETCPUFREQ(CLK_48M); | |
270 | ||
271 | USE_USB_INTS(); | |
272 | ||
273 | /* TODO: Does the order of the following lines matter? */ | |
274 | ENABLE_SUDAV(); | |
cfeb1a36 | 275 | ENABLE_EP2IBN(); |
d5f5ea73 UH |
276 | ENABLE_HISPEED(); |
277 | ENABLE_USBRESET(); | |
278 | ||
553c0ee3 MK |
279 | LED_INIT(); |
280 | LED_ON(); | |
cf43e09a UH |
281 | |
282 | /* Init timer2. */ | |
283 | RCAP2L = -500 & 0xff; | |
284 | RCAP2H = (-500 & 0xff00) >> 8; | |
285 | T2CON = 0; | |
286 | ET2 = 1; | |
287 | TR2 = 1; | |
288 | ||
d5f5ea73 UH |
289 | /* Global (8051) interrupt enable. */ |
290 | EA = 1; | |
291 | ||
292 | /* Setup the endpoints. */ | |
293 | setup_endpoints(); | |
294 | ||
295 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
296 | gpif_init_la(); | |
1cbff47d | 297 | } |
d5f5ea73 | 298 | |
28d52f41 | 299 | void fx2lafw_poll(void) |
1cbff47d JH |
300 | { |
301 | if (got_sud) { | |
302 | handle_setupdata(); | |
303 | got_sud = FALSE; | |
d5f5ea73 | 304 | } |
2846a114 JH |
305 | |
306 | if (vendor_command) { | |
307 | switch (vendor_command) { | |
2846a114 | 308 | case CMD_START: |
cd29817d | 309 | if ((EP0CS & bmEPBUSY) != 0) |
2846a114 JH |
310 | break; |
311 | ||
75630581 | 312 | if (EP0BCL == sizeof(struct cmd_start_acquisition)) { |
cfeb1a36 | 313 | gpif_acquisition_prepare( |
cd29817d | 314 | (const struct cmd_start_acquisition *)EP0BUF); |
2846a114 JH |
315 | } |
316 | ||
317 | /* Acknowledge the vendor command. */ | |
318 | vendor_command = 0; | |
319 | break; | |
2846a114 JH |
320 | default: |
321 | /* Unimplemented command. */ | |
322 | vendor_command = 0; | |
323 | break; | |
324 | } | |
325 | } | |
293d7e9e JH |
326 | |
327 | gpif_poll(); | |
d5f5ea73 | 328 | } |
f7f91781 JH |
329 | |
330 | void main(void) | |
331 | { | |
332 | fx2lafw_init(); | |
333 | while (1) | |
334 | fx2lafw_poll(); | |
335 | } |