|Name||IEEE 802.3 MII Management Interface|
|Description||Two wire clocked bidirectional signal|
The mdio protocol decoder supports the Management Data Input and Output protocol. This is a bidirection, single master protocol. It's also known SMI (Serial Management Interface), or as the MII Management layer.
The goal is to allow communication of settings and status between an Ethernet PHY and some device that needs Ethernet connectivity (the MAC).
It's defined in the IEE 802.3 standard. This standard is available for free from IEEE, but you do need to register to download it. It's defined (amongst other things) in chapter 22.
The protocol defines how to read and write registers. Registers 0-15 are defined by the standard, and 16-31 are left free for a specific PHY to have specific settings. These should be described in the PHY's datasheet.
The clock line (MDC) goes between 0 and the chip's logic level. The data from the MDIO signal is read on the clock rising edge. A high voltage is read as a 1, and a low voltage as a 0.
The MAC provides the clock signal. The clock should be a maximum of 2.5 MHz (although a lot of PHY's will accept faster clocks), but can be as slow as you want and doesn't need to be a stable frequency.
There should be a pullup on the MDIO signal. To start a message, the MAC takes over writing on the MDIO. If it's a read command, control of the MDIO is given to the PHY during the "turnaround".
The frame structure is defined in chapter 220.127.116.11 of the standard. A message is structured as follows:
- there are first 32 high bits. Some PHY's allow this to be shorter under certain conditions, but this isn't supported by the logic analyzer.
- Start of frame
- this is a 0,1 pattern
- Operation code
- 1,0 for a "read" message, 1,0 for a "write".
- PHY address
- 5 bits to select the PHY being addressed. Under certain contexts 0 is a broadcast address, check your PHY's datasheet.
- Register address
- 5 bits to select the address. Usually all registers are in the PHY's datasheet, and 0-15 are also described in the standard in chapter 22.2.4.
- 1,0 signal to give the PHY the chance to take over the MDIO line (in the case of a read) and to make sure there are never 32 consecutive ones within a valid message
- 16 data bits
Logic analyzer requirements
According to the protocol the maximum clock speed is 2.5 MHz (400 ns per clock cycle), but some PHY's allow faster speeds.
According to the standard, the MDIO only needs to be stable for 10 ns around the rising clock. This means that although the clock signal is in theory only 2.5 MHz, you might need a much faster logic analyzer to actually read the signal. 100 MHz or more is recommended.