Hantek 6022BL
Revision as of 23:40, 9 April 2017 by Uwe Hermann (talk | contribs)
 | |
| Status | supported |
|---|---|
| Source code | hantek-6xxx |
| Channels | 2 |
| Samplerate | 48MHz |
| Analog bandwidth | 20MHz |
| Vertical resolution | 8bit |
| Triggers | none (SW-only) |
| Input impedance | 1MΩ‖25pF |
| Memory | none |
| Display | none |
| Connectivity | USB |
| Website | hantek.com |
The Hantek 6022BL is a USB-based, 2-channel oscilloscope with an analog bandwidth of 20MS/s and 48MS/s sampling rate, and an 8-/16-channel logic analyzer with 24MHz sampling rate.
The device can either be used as oscilloscope or as logic analyzer, but not both at the same time. I.e., it is not a mixed-signal-oscilloscope (MSO).
Currently only the 8-channel logic analyzer mode is supported.
See Hantek 6022BL/Info for more details (such as lsusb -v output) about the device.
Hardware
- USB: Cypress CY7C68013A-100AXC (FX2LP) (datasheet)
- 256-byte I²C EEPROM: 2x Microchip 24LC02BI (datasheet)
- 16-Bit bus transceiver with 3-state outputs: TI SN74LVC16245A (datasheet)
- 8-channel analog mux/demux: 2x NXP 74HC4051D (datasheet)
- 1A low-dropout voltage regulator (3.3V): Advanced Monolithic Systems AMS1117-3.3 datasheet)
- 2W, fixed input, isolated & unregulated dual/single output DC/DC converter: Mornsun A_S-2WR2 (A0505S-2WR2) (datasheet)
- ADC: (educated guess, IC covered by glued-on heatsink)
- 8-bit, 40/80/100MHz, dual ADC: Analog Devices AD9288 (datasheet), or
- 8-bit, 100MHz, dual ADC: MXTronix MXT2088 (datasheet)
- 1.4GHz current feedback amplifiers with enable: 2x Intersil EL5166 (datasheet)
- 145 MHz FastFET Opamps: 2x AD8065: (datasheet), markings "HRA"
- Crystal: 24MHz
- Probes: 2x PP80B 1X/10X 80MHz bandwidth oscilloscope probes
- Attenuator: Hantek HT-201 20:1 attenuator (10MHz bandwidth, 1.053M input resistance)
The device has a "H/P" button. Depending on whether or not it's pressed it comes up with different USB VID/PIDs:
- Pressed: 04b4:602a Cypress Semiconductor Corp. (used for oscilloscope mode)
- Not pressed: 0925:3881 Lakeview Research Saleae Logic (Saleae Logic VID/PID, so fx2lafw works out of the box)
NXP 74HC4051D (upper/lower, CH1/CH2) pinout:
|
|
| S2 | S1 | S0 | 74HC4051D Mux | VDIVs (vendor software) |
|---|---|---|---|---|
| 0 | 0 | 0 | Y0 to Z | 200mV |
| 0 | 0 | 1 | Y1 to Z | 500mV |
| 0 | 1 | 0 | Y2 to Z | 5V, 2V, 1V |
| 0 | 1 | 1 | Y3 to Z | 100mV, 50mV, 20mV |
Intersil EL5166 (both) pinout:
| NC | 1- | O | -8 | CE# |
| (upper/lower 74HC4051D, Z) IN- | 2- | -7 | VS+ | |
| (AD8065, IN-/VOUT) IN+ | 3- | -6 | OUT | |
| VS- | 4- | -5 | NC |
Microchip 24LC02BI (both) pinout:
| (Low, but not GND) A0 | 1- | O | -8 | VCC |
| (GND) A1 | 2- | -7 | WP (GND) | |
| (GND) A2 | 3- | -6 | SCL (FX2 SCL) | |
| VSS | 4- | -5 | SDA (FX2 SDA) |
Analog Devices ADS9288 pinout:
| AD9288 pins | Description |
|---|---|
| S1, S2 | S1=VCC, S2=GND. "Normal operation, data align disabled". |
| DFS | Tied to GND. Data format select = "offset binary" (not "twos complement"). |
| AINA, AINB | Analog input channels. |
Cypress FX2 pinout:
| FX2 pins | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTL0 | Connected to AD9288 ENCA and ENCB and FX2 IFCLK. | |||||||||||||||
| PB0-PB7 | Connected to AD9288 D0A-D7A. | |||||||||||||||
| PD0-PD7 | Connected to AD9288 D0B-D7B. | |||||||||||||||
| PC2 | 1kHz probe calibration pin. | |||||||||||||||
| PC0/PC1 | Dual-color (red/green) LED.
|
Discovered connections:
- U2 is the Cypress FX2 controller, U4 is the '245 input buffer for digital probes, U8 is the ADC for two analog channels
- FX2 PB and PD are connected to 16 lines of input data (shared among the digital buffer and the ADC output)
- FX2 PA7 (pin 74) is directly connected to the digital buffer's OE signals (pins 25 and 48, low active, both 8bit groups share the signal) as well as DIR (pins 1 and 24)
- FX2 PA7 is also connected to the ADC's S1 signal (pin 8, via two discrete inverters with R37, Q2, R13, Q1), S2 (pin 9) is tied to GND
- according to the ADC datasheet (table 4), low/high signals on S1 and low on S2 result in either "standby mode" or "normal operation", respectively
- with the digital buffer's OE signal being low active, low/high results in "active" and "tristate", respectively
- this means: PA7 selects between digital (low) and analog (high) data paths, data is always at ports PB and PD, and either carries 16 digital channels, or two eight bit analog channels (TODO: work out the mapping of PB/PD bits to channel numbers)
- FX2 -> U4
- PD0 -> 2A1
- ...
- PD7 -> 2A8
- PB0 -> 1A7
- ...
- PB7 -> 1A8
- FX2 -> U4
- the benefit of "variable DIR" in the digital buffer is questionable, since it shares the signal with OE and for high levels the output is high-Z anyway -- so the ADC output is _not_ routed to digital pins when PA7 is high, not tying DIR to a fixed level is pointless(?)
- six PA lines of the FX2 are connected to three lines per analog channel each (4051 mux chips in the BNC to ADC path) for attenuation / gain control:
- FX2 -> U6:
- PA1 -> S0
- PA2 -> S1
- PA3 -> S2
- FX2 -> U10:
- PA4 -> S0
- PA5 -> S1
- PA6 -> S2
- FX2 -> U6:
- The LED is connected to PC0 and PC1
- The CAL is connected to PC2
Photos
Protocol
When the "H/P" button is not pressed, the device can be used as 8-channel 24MHz logic analyzer via fx2lafw out of the box (using the fx2lafw protocol).