Protocol decoder:parallel
Revision as of 15:55, 3 August 2014 by Uwe Hermann (talk | contribs)
 | |
| Name | Parallel |
|---|---|
| Description | Generic parallel synchronous bus |
| Status | supported |
| License | GPLv2+ |
| Source code | decoders/parallel |
| Input | logic |
| Output | parallel |
| Probes | — |
| Optional probes | CLK, D0-D63 |
The parallel protocol decoder can decode synchronous parallel buses with various number of data bits/probes and one clock line.
Hardware
TODO.
Protocol
On either the falling or rising clock edge one or more data lines (D0 up to possibly D63, for example) are sampled, and the individual probe values are combined to a number that is shown.