Saleae Logic
The Saleae Logic is a 24MHz, 8-channel, USB-based logic analyzer.
The unit itself is very small, and has a USB 2.0 port connecting it to a PC (and powering the unit) and a connector for the 8 + 1 probe set. It is built around a Cypress EZ-USB FX2LP microcontroller — an 8051-compatible chip with built-in USB 2.0 controller. It can sample 8 channels up to 24MHz and sells for $150.
See Saleae Logic/Info for more details (such as lsusb -vvv output) about the device.
See Saleae Logic16 for the successor product of the Saleae Logic.
Protocol
The Saleae Logic reports on the USB bus with vendor ID 0x0925, product ID 0x3881 (see also the full lsusb). It has no firmware on board; this must be uploaded when the unit is powered on. The standard procedure for the FX2LP chip is used for this. After the firmware is on board, the chip resets and announces itself on the USB bus with the same vendor and product IDs, but this time with only two endpoints: endpoint 1 (out) is used for sending commands to the logic analyzer, endpoint 2 (in) is for transfers of sample sets. Both endpoints are of type bulk.
The Saleae Logic does no analysis in hardware at all. Processing triggers, protocol analysis and so on is all done on the software side; the hardware unit merely sends the requested number of samples at a given sample rate. The device has 8 probes, all of which are always probed and sent along. A full sample is thus always exactly one byte.
Setting the samplerate, starting an acquisition
There is only one command the software sends to the Saleae Logic on endpoint 1: a two-byte command to set the samplerate. The first byte is always 0x01. This is likely a command opcode meaning "set sample rate".
The second byte indicates the samplerate. The samplerate is given in the form of a divider based on the FX2LP's clock, which runs at 48MHz. The following formula is used:
samplerate = 48 / (1 + divider)
Thus, a samplerate of 2 MHz (for example) is selected by using 23 as the divider:
| 1st byte | 2nd byte |
|---|---|
| 0x01 (1) | 0x17 (23) |
The following sample rates are supported:
| Samplerate | Divider |
|---|---|
| 200 kHz | 239 |
| 250 kHz | 191 |
| 500 kHz | 95 |
| 1 MHz | 47 |
| 2 MHz | 23 |
| 4 MHz | 11 |
| 8 MHz | 5 |
| 12 MHz | 3 |
| 16 MHz | 2 |
| 24 MHz | 1 |
Getting samples
Samples are read off endpoint 2. The Saleae Logic receives a read request from the host, and responds by sending the requested number of samples. The maximum number of samples transferred at a time is 4096, a constraint in the USB protocol. A sample is one byte, with each bit representing the state of one of the probes. Probe 1 (black wire) is in the MSB of the sample, probe 8 (purple wire) is the LSB.
Getting the firmware
The firmware required for the Cypress FX2 chip on the Saleae Logic is proprietary and can't be distributed with sigrok. But if you have a Saleae Logic, you can go and download the official software, install it somewhere (e.g. using wine) and/or extract the required data (e.g. using cabextract). Unfortunately the firmware doesn't exist as a separate file, it's embedded in a file named WinUSBLogicInterface.dll or USBDeviceInterface.dll.
The following lines must be used with the software 1.0.33 Beta for WinXP/Vista/7:
$ cabextract Logic\ Setup\ Beta.exe $ dd if=WinUSBLogicInterface.dll of=fw.hex skip=8036 count=17366 bs=1
The following lines must be used with the software 1.0.21 for WinXP/Vista/7.
$ cabextract Logic\ Setup.exe $ dd if=USBDeviceInterface.dll of=fw.hex skip=4220 count=17366 bs=1
Then:
$ objcopy -Iihex fw.hex -Obinary saleae-logic.fw
The resulting saleae-logic.fw file is usable by sigrok directly, just copy it into the /usr/local/share/libsigrok/firmware directory (may differ if you used the --prefix option of configure).
Random notes
The case has four Torx T2 screws you need to remove in order to be able to open it.