Difference between revisions of "Main Page"

Revision as of 18:22, 28 April 2010

The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL.

Design goals

Broad hardware support. Supports a wide variety of logic analyzers from various vendors with different capabilities.
Cross-platform. Works on Linux, Mac OS X and Windows, and on many architectures including x86, ARM, Sparc and PowerPC.
Scriptable protocol decoding. Extendable with protocol decoders and analyzers written in Python.
Format support. Supports various input and output formats (raw, ASCII, hex, CSV, gnuplot, VCD, others).

Supported hardware

Saleae Logic
(supported)
EE Electronics XLA/ESLA100 (supported)
ASIX SIGMA (partially supported)
Open workbench logic sniffer.jpg

Openbench Logic Sniffer
(work in progress)
ZEROPLUS Logic Cube LAP-C (work in progress)
CWAV USBee SX
(coming up)
Braintechnology USB-LPS
(planned)
Buspirate v3.jpg

Buspirate
(planned)
Intronix Logicport
(planned)

Documentation

Development

Getting in touch

Mailing lists: sigrok-devel (archive), sigrok-commits
IRC: #sigrok on Freenode
identi.ca: sigrok group
Sites: SF, Fm, ohloh, del.icio.us
Press
Logo

sigrok-gui on Linux

News

2010/04/06: VCD and Gnuplot output
2010/04/01: ZEROPLUS Logic Cube LAP-C support
2010/03/30: libsigrokdecode started
2010/03/19: GUI: i18n support
2010/03/17: Session save support
2010/03/16: GUI started
2010/03/14: Official project start

IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released to the CC-BY-SA 3.0. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!

@@ Line 17: / Line 17: @@
 File:Saleae Logic.jpg|<small>'''[[Saleae Logic]]'''<br />(supported)</small>
 File:Eeelec xla esla100.jpg|<small>'''[[EE Electronics XLA ESLA100|EE Electronics XLA/ESLA100]]''' (supported)</small>
+File:Sigma.jpg|<small>'''[[ASIX SIGMA]]''' (partially supported)</small>
 File:Open workbench logic sniffer.jpg|<small>'''[[Openbench Logic Sniffer]]'''<br />(work in progress)</small>
 File:Zeroplus Logic Cube.jpg|<small>'''[[ZEROPLUS Logic Cube LAP-C]]''' (work in progress)</small>
-File:Sigma.jpg|<small>'''[[ASIX SIGMA]]''' (work in progress)</small>
 File:Cwav usbee sx.jpg|<small>'''[[CWAV USBee SX]]'''<br />(coming up)</small>
 File:Braintechnology usb lps.jpg|<small>'''[[Braintechnology USB-LPS]]'''<br />(planned)</small>