Difference between revisions of "Fx2lafw"
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(Eliminated crystal frequency. All fx2s must have 24MHz xtal) |
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!Device | !Device | ||
!Probes (pins) | !Probes (pins) | ||
!FX2 package | !FX2 package | ||
!Buffer/ESD-protection | !Buffer/ESD-protection | ||
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| [[Saleae Logic]] | | [[Saleae Logic]] | ||
| 8 (PB0-PB7) | | 8 (PB0-PB7) | ||
| 56PVXC (SSOP) | | 56PVXC (SSOP) | ||
| ST DVIULC6-4SC6 | | ST DVIULC6-4SC6 | ||
Line 33: | Line 31: | ||
| [[EE Electronics XLA ESLA100]] | | [[EE Electronics XLA ESLA100]] | ||
| 8 (PB0-PB7) | | 8 (PB0-PB7) | ||
| 56LFXC (QFN) | | 56LFXC (QFN) | ||
| NXP 74HC245D | | NXP 74HC245D | ||
Line 42: | Line 39: | ||
| [[CWAV USBee SX]] | | [[CWAV USBee SX]] | ||
| 8 (PB0-PB7) | | 8 (PB0-PB7) | ||
| 56PVXC (SSOP) | | 56PVXC (SSOP) | ||
| none | | none | ||
Line 51: | Line 47: | ||
| [[Lcsoft Mini Board]] | | [[Lcsoft Mini Board]] | ||
| 16 (PB0-PB7, PD0-PD7) | | 16 (PB0-PB7, PD0-PD7) | ||
| 56PVXC (SSOP) | | 56PVXC (SSOP) | ||
| none | | none | ||
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|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| [[CWAV USBee AX]] | | [[CWAV USBee AX]] | ||
| ? | | ? | ||
| ? | | ? | ||
Line 69: | Line 63: | ||
| [[EE Electronics ESLA201A]] | | [[EE Electronics ESLA201A]] | ||
| 8 digital (PB0-PB7), 8 analog (PD0-PD7) | | 8 digital (PB0-PB7), 8 analog (PD0-PD7) | ||
| 56LFXC (QFN) | | 56LFXC (QFN) | ||
| none | | none | ||
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| [[Braintechnology USB-LPS]] | | [[Braintechnology USB-LPS]] | ||
| 16 | | 16 | ||
| 56PVXC (SSOP) | | 56PVXC (SSOP) | ||
| none | | none | ||
Line 87: | Line 79: | ||
| [[Robomotic MiniLogic]] | | [[Robomotic MiniLogic]] | ||
| 8 | | 8 | ||
| ? | | ? | ||
| ? | | ? |
Revision as of 13:31, 19 February 2012
fx2lafw is an open-source firmware for Cypress FX2 chips which makes them usable as simple logic analyzer hardware.
It is licensed under the terms of the GNU GPL (version 2, or later) and written in C, using sdcc as compiler, and fx2lib as helper library.
Note: This is work in progress. It does NOT work, yet!
Hardware overview
The fx2lafw firmware is meant to work on any FX2-based hardware, including logic analyzers, FX2 eval boards, or other hardware which has this chip on-board.
Here's a quick overview of some of the relevant hardware information we have about the various devices:
Device | Probes (pins) | FX2 package | Buffer/ESD-protection | Resistor per probe | I2C EEPROM |
---|---|---|---|---|---|
Saleae Logic | 8 (PB0-PB7) | 56PVXC (SSOP) | ST DVIULC6-4SC6 | ? Ω | ? |
EE Electronics XLA ESLA100 | 8 (PB0-PB7) | 56LFXC (QFN) | NXP 74HC245D | 100 Ω | Atmel ATMLH911 02B 1 |
CWAV USBee SX | 8 (PB0-PB7) | 56PVXC (SSOP) | none | 560 Ω | Microchip 24LC01B |
Lcsoft Mini Board | 16 (PB0-PB7, PD0-PD7) | 56PVXC (SSOP) | none | none | Shenzhen First-Rank Technology T24C128A |
CWAV USBee AX | ? | ? | ? | ? Ω | ? |
EE Electronics ESLA201A | 8 digital (PB0-PB7), 8 analog (PD0-PD7) | 56LFXC (QFN) | none | 100 Ω | Atmel ATMLH113 |
Braintechnology USB-LPS | 16 | 56PVXC (SSOP) | none | ? 68 Ω | Atmel ATML0816 TINY13 20SU |
Robomotic MiniLogic | 8 | ? | ? | ? Ω | ? |
Download
$ git clone git://sigrok.git.sourceforge.net/gitroot/sigrok/fx2lafw
Building
$ cd fx2lafw $ git clone git://github.com/mulicheng/fx2lib.git $ make
Usage
$ cycfx2prog -id=vvvv:pppp prg:build/fx2lafw.ihx reset run delay:100
You have to provide the USB VID/PID of the FX2 device (before firmware upload) using the -id parameter.
Resources
- sdcc (C compiler for 8051 microcontrollers, usable for FX2)
- fx2lib: SF project page, blog article, github repo, mailing list
- Cypress FX2 docs:
- CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A datasheet (PDF)
- EZ-USB Technical Reference Manual (TRM) (PDF)
- EZ-USB FX2LP appnotes
- EZ-USB FX2LP errata
- GPIF Designer (Windows software, requires login)
- CY3681 EZ-USB FX2 Development Kit (GPIF designer downloadable without login)