Difference between revisions of "ZEROPLUS Logic Cube LAP-C(16032)"
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File:Zeroplus_LAPC16032_highres_top.jpg|<small>PCB, top</small> | File:Zeroplus_LAPC16032_highres_top.jpg|<small>PCB, top</small> | ||
File:Zeroplus_LAPC16032_highres_bottom.jpg|<small>PCB, bottom</small> | File:Zeroplus_LAPC16032_highres_bottom.jpg|<small>PCB, bottom</small> | ||
</gallery> | </gallery> | ||
Latest revision as of 15:20, 25 December 2017
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| Status | supported |
|---|---|
| Source code | zeroplus-logic-cube |
| Channels | 16 |
| Samplerate | 100MHz |
| Samplerate (state) | 100MHz |
| Triggers | pattern, edge |
| Min/max voltage | -6V — +6V |
| Memory | 32Kbits/channel |
| Compression | yes ("max 8Mbits") |
| Website | zeroplus.com.tw |
The ZEROPLUS Logic Cube LAP-C(16032) is a USB-based, 16-channel logic analyzer with up to 100MHz samplerate.
See ZEROPLUS Logic Cube LAP-C(16032)/Info for some more details (such as lsusb -v output) on the device.
See ZEROPLUS Logic Cube LAP-C series for information common to all devices in this series.
Hardware
- Cypress CY7C1347G-250AXC (4Mbit pipelined sync SRAM, 250MHz)
See ZEROPLUS_Logic_Cube_LAP-C_series#Hardware for the hardware parts that are common to all devices in this series.
Photos
Package, front
Package, back
Package contents
Device
Device with probes
Pins / connector
PCB, front
PCB, back
Another model:
PCB, top
Yet another model:
PCB, top
PCB, bottom
Protocol
See ZEROPLUS_Logic_Cube_LAP-C_series#Protocol.