Difference between revisions of "File format:Vcd"
Jump to navigation
Jump to search
(implementation, list available options, mention current limitations) |
|||
| Line 23: | Line 23: | ||
== Implementation == | == Implementation == | ||
These are the input module's options and their default values: | |||
$ sigrok-cli -I vcd --show | |||
ID: vcd | |||
Name: VCD | |||
Description: Value Change Dump data | |||
Options: | |||
numchannels: The number of (logic) channels in the data (default 0) | |||
skip: Skip samples until the specified timestamp; < 0: Skip until first timestamp listed; 0: Don't skip (default -1) | |||
downsample: Downsample, i.e. divide the samplerate by the specified factor (default 1) | |||
compress: Compress idle periods longer than the specified value (default 0) | |||
Interpretation: | |||
* The number of channels gets auto-determined by the software, but can get overridden by user specs (limited to a smaller number). | |||
* By default all input data gets processed, users can specify that a leading part of the input shall get skipped. | |||
* The sigrok software will use the input file's sample count and timescale values, which _can_ result in excessive memory consumption. Some generators love to specify insane timescales which results in large sample numbers. The '''downscale''' option allows to workaround that implementation detail. | |||
* The sigrok software will provide lots of samples for extended periods of time when the input signal has these idle periods. Users can request to have these periods shortened. | |||
There are some limitations in the current VCD input module implementation: | |||
* Support for nested name spaces is missing ('module' keyword). | |||
* Exclusive support for single-bit logic data ('wire 1' or 'reg 1'). No support for bit vectors, integer or real numbers. | |||
* The total number of channels may be limited (single letter names, which results in some 94 supported names or so). | |||
== Examples == | == Examples == | ||
Revision as of 06:52, 27 October 2019
| Name | Value change dump |
|---|---|
| Status | supported |
| Source code (in) | vcd.c |
| Source code (out) | vcd.c |
| Common extension(s) | .vcd, .wave |
| MIME type | — |
| ASCII format | yes |
| Compression | yes (only stores transitions) |
| Website | wikipedia.org |
vcd is an ASCII-based file format that...
It can be opened and processed e.g. in a waveform viewer software.
Format
See Wikipedia for a short overview.
Properties
Implementation
These are the input module's options and their default values:
$ sigrok-cli -I vcd --show ID: vcd Name: VCD Description: Value Change Dump data Options: numchannels: The number of (logic) channels in the data (default 0) skip: Skip samples until the specified timestamp; < 0: Skip until first timestamp listed; 0: Don't skip (default -1) downsample: Downsample, i.e. divide the samplerate by the specified factor (default 1) compress: Compress idle periods longer than the specified value (default 0)
Interpretation:
- The number of channels gets auto-determined by the software, but can get overridden by user specs (limited to a smaller number).
- By default all input data gets processed, users can specify that a leading part of the input shall get skipped.
- The sigrok software will use the input file's sample count and timescale values, which _can_ result in excessive memory consumption. Some generators love to specify insane timescales which results in large sample numbers. The downscale option allows to workaround that implementation detail.
- The sigrok software will provide lots of samples for extended periods of time when the input signal has these idle periods. Users can request to have these periods shortened.
There are some limitations in the current VCD input module implementation:
- Support for nested name spaces is missing ('module' keyword).
- Exclusive support for single-bit logic data ('wire 1' or 'reg 1'). No support for bit vectors, integer or real numbers.
- The total number of channels may be limited (single letter names, which results in some 94 supported names or so).
Examples
$date Fri Aug 1 23:46:38 2014 $end $version libsigrok 0.3.0 $end $comment Acquisition with 2/8 channels at 500 kHz $end $timescale 1 us $end $scope module libsigrok $end $var wire 1 ! sda $end $var wire 1 " scl $end $upscope $end $enddefinitions $end #0 1! 0" #40 0! #72 1" #102 1! #144 0! #174 0" #204 1! #246 0! #276 1" #306 1! #348 0! #380 0" #410 1! #452 0! #514 1! #566 0! #628 1! #668 0! #730 1! #770 0! #832 1! #872 0! #938 1! #978 0! 1" #1010 0" #1040 1! [...] #106772 1! #106812 0! #106844 0" #106874 1! #106914 1" #160000