Difference between revisions of "Protocol decoder:Z80"
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| description = Zilog Z80 microprocessor disassembly | | description = Zilog Z80 microprocessor disassembly | ||
| status = <span style="background-color: lime">supported</span> | | status = <span style="background-color: lime">supported</span> | ||
| license = | | license = GPLv3+ | ||
| source_code_dir = z80 | | source_code_dir = z80 | ||
| image = [[File:Z80 decoder example.png|250px]] | | image = [[File:Z80 decoder example.png|250px]] | ||
Revision as of 13:23, 2 March 2014
 | |
| Name | Z80 |
|---|---|
| Description | Zilog Z80 microprocessor disassembly |
| Status | supported |
| License | GPLv3+ |
| Source code | decoders/z80 |
| Input | logic |
| Output | z80 |
| Probes | D0–D7, /M1, /RD, /WR |
| Optional probes | /MREQ, /IORQ, A0–A15 |
The z80 protocol decoder disassembles the instruction stream of a Zilog Z80 microprocessor.
Hardware
KC 85/4
The z80/kc85 directory in sigrok-dumps contains a set of example bus captures of the Z80-based KC 85/4 computer.
The logic analyzer used was a Sysclk LWLA1034.
Protocol
The data bus lines plus the control signals /M1, /RD and /WR are sufficient to display full disassembly. Optionally, the address bus lines and the control signals /MREQ and /IORQ may also be provided.