Difference between revisions of "Braintechnology USB Interface V2.x"
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| samplerate_state = — | | samplerate_state = — | ||
| triggers = none (SW-only) | | triggers = none (SW-only) | ||
| voltages = | | voltages = -0.5V — 5.25V | ||
| threshold = Fixed: VIH=2.0V—5.25V, VIL=-0.5V—0.8V | |||
| memory = none | | memory = none | ||
| compression = none | | compression = none | ||
Latest revision as of 12:08, 28 July 2013
 | |
| Status | supported |
|---|---|
| Source code | fx2lafw |
| Channels | 8/16 |
| Samplerate | 24MHz |
| Samplerate (state) | — |
| Triggers | none (SW-only) |
| Min/max voltage | -0.5V — 5.25V |
| Threshold voltage | Fixed: VIH=2.0V—5.25V, VIL=-0.5V—0.8V |
| Memory | none |
| Compression | none |
| Website | braintechnology.de |
The Braintechnology USB Interface V2.x is a Cypress FX2 eval board, which can be used as USB-based, 16-channel logic analyzer with up to 24MHz sampling rate.
There are various revisions of the hardware, e.g. V2.5, V2.6, and V2.7.
In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.
See Braintechnology USB Interface V2.x/Info for some more details (such as lsusb -vvv output) on the device.
Hardware
- Main chip: Cypress CY7C68013A-56PVXC (FX2LP)
- 64kB I2C EEPROM: Microchip 24LC641
- Low-dropout voltage regulator: ST LD33
- Crystal: 24MHz
- ?: PDEI
Photos
PCB, front
PCB, back
Cypress FX2LP
I2C EEPROM, LDO
PDEI chip
Protocol
Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.