Difference between revisions of "ChronoVu LA16"
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| image = [[File:Chronovu la16.png|180px]] | | image = [[File:Chronovu la16.png|180px]] | ||
| name = ChronoVu LA16 | | name = ChronoVu LA16 | ||
| status = | | status = supported | ||
| source_code_dir = | | source_code_dir = chronovu-la | ||
| channels = 16 | | channels = 16 | ||
| samplerate = 200MHz | | samplerate = 200MHz | ||
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}} | }} | ||
The '''ChronoVu LA16''' is a USB-based 16-channel logic analyzer with up to 200MHz sampling rate. | The '''ChronoVu LA16''' is a USB-based 16-channel logic analyzer with up to 200MHz sampling rate. See [[ChronoVu LA8]] for an 8 channel version. | ||
It features a Xilinx FPGA for sampling, 8MByte of built-in SDRAM to store the samples, and can trigger on low/high/any state or rising/falling/any edge of any combination of probes. After the 8MByte sample buffer is full, the data is transferred to the host via an FTDI FT245RL chip. | It features a Xilinx FPGA for sampling, 8MByte of built-in SDRAM to store the samples, and can trigger on low/high/any state or rising/falling/any edge of any combination of probes. After the 8MByte sample buffer is full, the data is transferred to the host via an FTDI FT245RL chip. | ||
See [[ChronoVu LA16/Info]] for more details (such as '''lsusb - | See [[ChronoVu LA16/Info]] for more details (such as '''lsusb -v''' output) about the device. | ||
<em style="color:green"> | <em style="color:green"> | ||
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== Protocol == | == Protocol == | ||
Similar to the [[ChronoVu_LA8#Protocol|ChonoVu LA8 protocol]], more info will follow. | |||
== Resources == | == Resources == | ||
* [http://www.chronovu.com/downloads/ReadMeFile%20LA16-4.00.pdf Manual] | |||
* [http://www.chronovu.com/help/docs/faq/ Vendor FAQ] | |||
* [http://www.chronovu.com/download/ Vendor software] | |||
[[Category:Device]] | [[Category:Device]] | ||
[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category: | [[Category:Supported]] | ||
Latest revision as of 17:36, 24 May 2018
 | |
| Status | supported |
|---|---|
| Source code | chronovu-la |
| Channels | 16 |
| Samplerate | 200MHz |
| Samplerate (state) | — |
| Triggers | high/low/any state, rising/falling/any edge |
| Min/max voltage | -0.5 — 6V |
| Threshold voltage | Fixed: VIH=2V—5.5V, VIL=0V—0.8V |
| Memory | 8Mbyte (SDRAM) |
| Compression | none |
| Website | chronovu.com |
The ChronoVu LA16 is a USB-based 16-channel logic analyzer with up to 200MHz sampling rate. See ChronoVu LA8 for an 8 channel version.
It features a Xilinx FPGA for sampling, 8MByte of built-in SDRAM to store the samples, and can trigger on low/high/any state or rising/falling/any edge of any combination of probes. After the 8MByte sample buffer is full, the data is transferred to the host via an FTDI FT245RL chip.
See ChronoVu LA16/Info for more details (such as lsusb -v output) about the device.
Many thanks to the vendor (ChronoVu) for freely providing information on the protocol used to communicate with the device. This helped us implement the libsigrok hardware driver more quickly. We're happy to see more open-source friendly vendors support sigrok!
Hardware
- Xilinx XC3S50AN
- Micron MT48LC2M32B2 SDRAM (8 MByte)
- FTDI FT245RL
- ...
Photos
TODO.
Protocol
Similar to the ChonoVu LA8 protocol, more info will follow.