Difference between revisions of "XZL Studio DX"

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{{DISPLAYTITLE:XZL_Studio DX}}
{{DISPLAYTITLE:XZL_Studio DX}}
{{Infobox logic analyzer
{{Infobox logic analyzer
| image            =  
| image            = [[File:Xzl studio-dx mugshot.png|180px]]
| name            = XZL_Studio DX
| name            = XZL_Studio DX
| status          = planned
| status          = supported
| source_code_dir  = fx2lafw
| source_code_dir  = fx2lafw
| channels        = 16 + 2
| channels        = 16 + 2
Line 21: Line 21:


See [[XZL_Studio DX/Info]] for some more details (such as '''lsusb -vvv''' output) on the device.
See [[XZL_Studio DX/Info]] for some more details (such as '''lsusb -vvv''' output) on the device.
'''Note''':You need to chose one of "CWAV USBee DX" devices found in system ( ''sigrok-ok --scan'' ). One of them is digital (supported, 16 channels). Other show 16 digital channels too, but it is for 2x analog input and not working yet.


'''Note''': Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!
'''Note''': Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!
'''Note''': Idea how sync 2 chips works. Second FX2 is responsible for reading ADC data only, but it can't initialise processing. It can only get info from first chip that he need to read data -> pin SLWR. So it means that if second chip do conversions only when triggered, then there are exactly that same number of samples read from both chips, from that same time... Look at 48 page of [http://www.cypress.com/?docID=45142#page=48 Cypress CY7C68013A-56LTXC (FX2LP)] "Slave FIFO Asynchronous Write"


== Hardware ==
== Hardware ==
Line 44: Line 48:
== Pin mapping ==
== Pin mapping ==


'''First CY7C68013A''' <br/>
Needed for use (I don't know how to remap pins yet)
Responsible for all digital inputs (0-15). Now it works with latest software version, but channels are scrambled:
 
Current PIN meaning - instead of that what is printed on device (for sigrok 0.8)
{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
|-
| 4 || 15
|-
| 5 || 14
|-
| 6 || 13
|-
| 7 || 8
|-
| 3 || 9
|-
| 2 || 10
|-
| 1 || 11
|-
| 0 || 12
|-
| TRIG || GND
|-
| 5V || GND
|-
|}
 
 
=== First FX2LP pin mappings ===
 
Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:


{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
Line 84: Line 117:
|-
|-
| 36 || CTL0/FLAGA || TRIG || socket pin
| 36 || CTL0/FLAGA || TRIG || socket pin
|-
| 37 || CTL1/*FLAGB || ADC [1,2] CLK + RDY1/SLWR on second FX2LP || signal for both ADC and secondary FX2
|-
|-
| 21 || Reserved || GND ||  
| 21 || Reserved || GND ||  
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Second CY7C68013A <br/>
=== Second FX2LP pin mappings ===


Connected to both ADCs <br/>
Connected to both ADCs <br/>
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! #        !!  Pin !! Destination !! Remark
! #        !!  Pin !! Destination !! Remark
|-
|-
| 9        || RDY1/SLWR    || ADC [1,2] CLK || ADC_clock, both ADC connected to single pin
| 9        || RDY1/SLWR    || CL1 on first FXLP and ADC [1,2] CLK || input: ADC_clock, signal to start read data
|-
|-
| 25-32    || FD0-FD7      || ADC CH1, D1-D8 || ADC_data for channel 1
| 25-32    || FD0-FD7      || ADC CH1, D1-D8 || ADC_data for channel 1
Line 110: Line 145:
|}
|}


TODO - check rest of the pins
''TODO'' - check rest of the pins


EEPROM - connected to both (!) CY7C68013A processors <br/>
EEPROM - connected to both (!) CY7C68013A processors <br/>
Line 123: Line 158:
|-
|-
|}
|}
TODO


== Photos ==
== Photos ==
Line 149: Line 182:
[[Category:Oscilloscope]]
[[Category:Oscilloscope]]
[[Category:Mixed-signal oscilloscope]]
[[Category:Mixed-signal oscilloscope]]
[[Category:Planned]]
[[Category:Supported]]

Latest revision as of 16:31, 29 October 2018

XZL_Studio DX
Xzl studio-dx mugshot.png
Status supported
Source code fx2lafw
Channels 16 + 2
Samplerate 24MHz
Samplerate (state) —
Triggers none (SW-only)
Min/max voltage Digital 0 — 5.4V
Analog ±10V
Threshold voltage Fixed: VIH=1.4V, VIL=0.8V
Memory none
Compression none
Website hotmcu.com

The XZL_Studio DX is a USB-based, 16-channel logic analyzer with up to 24MHz sampling rate, and with 2 additional analog channels.

It is a clone of the CWAV USBee DX.

See XZL_Studio DX/Info for some more details (such as lsusb -vvv output) on the device.

Note:You need to chose one of "CWAV USBee DX" devices found in system ( sigrok-ok --scan ). One of them is digital (supported, 16 channels). Other show 16 digital channels too, but it is for 2x analog input and not working yet.

Note: Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!

Note: Idea how sync 2 chips works. Second FX2 is responsible for reading ADC data only, but it can't initialise processing. It can only get info from first chip that he need to read data -> pin SLWR. So it means that if second chip do conversions only when triggered, then there are exactly that same number of samples read from both chips, from that same time... Look at 48 page of Cypress CY7C68013A-56LTXC (FX2LP) "Slave FIFO Asynchronous Write"

Hardware

Two jumpers:

  • P1 jumper - WRITE PROTECT, Connects WP EEPROM pin [7] to Vcc. If pin is closed, Write Protection is enabled.
  • P3 jumper - EEPROM CONNECTION, connects SDA EEPROM pin [5] to SDA pins on both CY7C68013A (if open there is no connection)

Extra info,
It looks that place for second eeprom is designed as backup memory. If P4 is closed, and P3 is open, then only spare memory is connected.

Pin mapping

Needed for use (I don't know how to remap pins yet)

Current PIN meaning - instead of that what is printed on device (for sigrok 0.8)

4 15
5 14
6 13
7 8
3 9
2 10
1 11
0 12
TRIG GND
5V GND


First FX2LP pin mappings

Responsible for all digital inputs (0-15) and TRIG. Now it works with latest software version, but channels numbers are scrambled:

# Pin Destination Remark
FD4 0 digital input
FD5 1 digital input
FD6 2 digital input
FD7 3 digital input
FD3 4 digital input
FD2 5 digital input
FD1 6 digital input
FD0 7 digital input
FD15 8 digital input
FD14 9 digital input
FD13 a digital input
FD8 b digital input
FD9 c digital input
FD10 d digital input
FD11 e digital input
FD12 f digital input
36 CTL0/FLAGA TRIG socket pin
37 CTL1/*FLAGB ADC [1,2] CLK + RDY1/SLWR on second FX2LP signal for both ADC and secondary FX2
21 Reserved GND


Second FX2LP pin mappings

Connected to both ADCs
FX2LP pin mappings

# Pin Destination Remark
9 RDY1/SLWR CL1 on first FXLP and ADC [1,2] CLK input: ADC_clock, signal to start read data
25-32 FD0-FD7 ADC CH1, D1-D8 ADC_data for channel 1
42-56,1-3 FD8-FD15 ADC CH2, D1-D8 ADC_data for channel 2
45 PA5/FIFOADR1 GND gnd ? to check
47 PA7/*FLAGD/SLCS# GND gnd ? to check? probably can be used do distinguish chips

TODO - check rest of the pins

EEPROM - connected to both (!) CY7C68013A processors

# EEPROM Processor
SDA SDA via jumper
SCL SCL

Photos

  • Device, top

  • Device, connectors

  • Device, usb

  • PCB, top

  • PCB, bottom

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources

TODO.

Retrieved from "https://sigrok.org/w/index.php?title=XZL_Studio_DX&oldid=13848"