Difference between revisions of "Hantek 6022BL"

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| connectivity        = USB
| connectivity        = USB
| features            =  
| features            =  
| price              = $73
| website            = [http://www.hantek.com/en/ProductDetail_2_153.html hantek.com]
| website            = [http://www.hantek.com/en/ProductDetail_2_153.html hantek.com]
}}
}}
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== Hardware ==
== Hardware ==


* '''USB''': [http://www.cypress.com/documentation/datasheets/cy7c68013a-cy7c68014a-cy7c68015a-cy7c68016a-ez-usb-fx2lp-usb Cypress CY7C68013A-100AXC] (FX2LP) ([http://www.cypress.com/file/138911/download datasheet])
* '''USB''': [http://www.cypress.com/documentation/datasheets/cy7c68013a-cy7c68014a-cy7c68015a-cy7c68016a-ez-usb-fx2lp-usb Cypress CY7C68013A-100AXC] (FX2LP) ([http://www.cypress.com/file/138911/download datasheet]) or Corebai CBM9002A ([http://corebai.com/en/UploadFiles/20211203/100008155.pdf datasheet])
* '''256-byte I²C EEPROM''': 2x [http://www.microchip.com/wwwproducts/en/24LC02B Microchip 24LC02BI] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''256-byte I²C EEPROM''': 2x [http://www.microchip.com/wwwproducts/en/24LC02B Microchip 24LC02BI] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet])
* '''16-Bit bus transceiver with 3-state outputs''': [http://www.ti.com/product/sn74lvc16245a TI SN74LVC16245A] ([http://www.ti.com/lit/ds/symlink/sn74lvc16245a.pdf datasheet])
* '''16-Bit bus transceiver with 3-state outputs''': [http://www.ti.com/product/sn74lvc16245a TI SN74LVC16245A] ([http://www.ti.com/lit/ds/symlink/sn74lvc16245a.pdf datasheet])
* '''8-channel analog mux/demux''': [http://www.nxp.com/products/discretes-and-logic/logic/8-channel-analog-multiplexer-demultiplexer:74HC4051D NXP 74HC4051D] ([http://cache.nxp.com/documents/data_sheet/74HC_HCT4051.pdf?pspll=1 datasheet])
* '''8-channel analog mux/demux''': 2x [http://www.nxp.com/products/discretes-and-logic/logic/8-channel-analog-multiplexer-demultiplexer:74HC4051D NXP 74HC4051D] ([http://cache.nxp.com/documents/data_sheet/74HC_HCT4051.pdf?pspll=1 datasheet])
* '''1A low-dropout voltage regulator (3.3V):''' [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] [http://www.advanced-monolithic.com/pdf/ds1117.pdf datasheet])
* '''1A low-dropout voltage regulator (3.3V):''' [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] [http://www.advanced-monolithic.com/pdf/ds1117.pdf datasheet])
* '''2W, fixed input, isolated & unregulated dual/single output DC/DC converter''': [http://www.mornsun.cn/html/product/content/A_S-2WR2.html Mornsun A_S-2WR2 (A0505S-2WR2)] ([http://www.mornsun.cn/uploads/pdf/A_S-2WR2.pdf datasheet])
* '''2W, fixed input, isolated & unregulated dual/single output DC/DC converter''': [http://www.mornsun.cn/html/product/content/A_S-2WR2.html Mornsun A_S-2WR2 (A0505S-2WR2)] ([http://www.mornsun.cn/uploads/pdf/A_S-2WR2.pdf datasheet])
* '''ADC''': ? MXT2088, AD9288 compatible? (pinout matches, though the chip might differ)
* '''ADC''': (educated guess, IC covered by glued-on heatsink)
* '''?''': S1661SZ B212FG
** '''8-bit, 40/80/100MHz, dual ADC''': [http://www.analog.com/en/products/analog-to-digital-converters/ad-converters/ad9288.html Analog Devices AD9288] ([http://www.analog.com/media/en/technical-documentation/data-sheets/AD9288.pdf datasheet]), or
** '''8-bit, 100MHz, dual ADC''': [https://translate.google.com/translate?hl=en&sl=zh-CN&tl=en&u=http%3A%2F%2Fwww.mxtronics.com%2Fn107%2Fn124%2Fn181%2Fn184%2Fc692%2Fcontent.html MXTronix MXT2088] ([http://www.mxtronics.com/n107/n124/n181/n184/c692/attr/2630.pdf datasheet])
* '''1.4GHz current feedback amplifiers with enable''': 2x [http://www.intersil.com/en/products/amplifiers-and-buffers/all-amplifiers/amplifiers/EL5166.html Intersil EL5166] ([http://www.intersil.com/content/dam/Intersil/documents/el51/el5166-67.pdf datasheet])
* '''145 MHz FastFET Opamps''': 2x [http://www.analog.com/en/products/amplifiers/operational-amplifiers/jfet-input-amplifiers/ad8065.html#product-overview AD8065]: ([http://www.analog.com/static/imported-files/data_sheets/AD8065_8066.pdf datasheet]), markings "HRA"
* '''Crystal''': 24MHz
* '''Crystal''': 24MHz
* '''Probes''': 2x PP80B 1X/10X 80MHz bandwidth oscilloscope probes
* '''Probes''': 2x PP80B 1X/10X 80MHz bandwidth oscilloscope probes
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* '''Not pressed''': [[Hantek_6022BL/Info|0925:3881 Lakeview Research Saleae Logic]] ([[Saleae Logic]] VID/PID, so [[fx2lafw]] works out of the box)
* '''Not pressed''': [[Hantek_6022BL/Info|0925:3881 Lakeview Research Saleae Logic]] ([[Saleae Logic]] VID/PID, so [[fx2lafw]] works out of the box)


Discovered connections:
'''NXP 74HC4051D (upper/lower, CH1/CH2) pinout''':
* U2 is the Cypress FX2 controller, U4 is the '245 input buffer for digital probes, U8 is the ADC for two analog channels
<small>
* FX2 PB and PD are connected to 16 lines of input data (shared among the digital buffer and the ADC output)
<table><tr><td>
* FX2 PA7 (pin 74) is directly connected to the digital buffer's OE signals (pins 25 and 48, low active, both 8bit groups share the signal) as well as DIR (pins 1 and 24)
{{chip_16pin
* FX2 PA7 is also connected to the ADC's S1 signal (pin 8, via two discrete inverters with R37, Q2, R13, Q1), S2 (pin 9) is tied to GND
|1=Y4
* according to the ADC datasheet (table 4), low/high signals on S1 and low on S2 result in either "standby mode" or "normal operation", respectively
|2=<span style="color:orange">(GND)</span> Y6
* with the digital buffer's OE signal being low active, low/high results in "active" and "tristate", respectively
|3=<span style="color:red">(upper EL5166, IN-)</span> Z
* this means: PA7 selects between digital (low) and analog (high) data paths, data is always at ports PB and PD, and either carries 16 digital channels, or two eight bit analog channels (TODO: work out the mapping of PB/PD bits to channel numbers)
|4=<span style="color:orange">(GND)</span> Y7
** FX2 -> U4
|5=<span style="color:orange">(GND)</span> Y5
*** PD0 -> 2A1
|6=<span style="color:orange">(GND)</span> E#
*** ...
|7=VEE
*** PD7 -> 2A8
|8=GND
*** PB0 -> 1A7
|9=S2 <span style="color:green">(FX2 PA3)</span>
*** ...
|10=S1 <span style="color:green">(FX2 PA2)</span>
*** PB7 -> 1A8
|11=S0 <span style="color:green">(FX2 PA1)</span>
* the benefit of "variable DIR" in the digital buffer is questionable, since it shares the signal with OE and for high levels the output is high-Z anyway -- so the ADC output is _not_ routed to digital pins when PA7 is high, not tying DIR to a fixed level is pointless(?)
|12=Y3
* six PA lines of the FX2 are connected to three lines per analog channel each (4051 mux chips in the BNC to ADC path) for attenuation / gain control:
|13=Y0
** FX2 -> U6:
|14=Y1
*** PA1 -> S0
|15=Y2
*** PA2 -> S1
|16=VCC
*** PA3 -> S2
}}
** FX2 -> U10:
</td><td>
*** PA4 -> S0
{{chip_16pin
*** PA5 -> S1
|1=<span style="color:orange">(GND)</span> Y4
*** PA6 -> S2
|2=<span style="color:orange">(GND)</span> Y6
* The LED is connected to PC0 and PC1
|3=<span style="color:red">(lower EL5166, IN-)</span> Z
* The CAL  is connected to PC2
|4=<span style="color:orange">(GND)</span> Y7
|5=<span style="color:orange">(GND)</span> Y5
|6=<span style="color:orange">(GND)</span> E#
|7=VEE
|8=GND
|9=S2 <span style="color:darkcyan">(FX2 PA6)</span>
|10=S1 <span style="color:darkcyan">(FX2 PA5)</span>
|11=S0 <span style="color:darkcyan">(FX2 PA4)</span>
|12=Y3
|13=Y0
|14=Y1
|15=Y2
|16=VCC
}}
</td></tr></table>
</small>
 
{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!S2
!S1
!S0
!74HC4051D Mux
!VDIVs (vendor software)
|-
| 0 || 0 || 0 || Y0 to Z || 200mV
|-
| 0 || 0 || 1 || Y1 to Z || 500mV
|-
| 0 || 1 || 0 || Y2 to Z || 5V, 2V, 1V
|-
| 0 || 1 || 1 || Y3 to Z || 100mV, 50mV, 20mV
|}
 
'''Intersil EL5166 (both) pinout''':
<small>
{{chip_8pin
|1=NC
|2=<span style="color:red">(upper/lower 74HC4051D, Z)</span> IN-
|3=<span style="color:blue">(AD8065, IN-/VOUT)</span> IN+
|4=VS-
|5=NC
|6=OUT
|7=VS+
|8=CE#
}}
</small>
 
'''Microchip 24LC02BI (both) pinout''':
<small>
{{chip_8pin
|1=<span style="color:orange">(Low, but not GND)</span> A0
|2=<span style="color:orange">(GND)</span> A1
|3=<span style="color:orange">(GND)</span> A2
|4=VSS
|5=SDA <span style="color:purple">(FX2 SDA)</span>
|6=SCL <span style="color:purple">(FX2 SCL)</span>
|7=WP <span style="color:orange">(GND)</span>
|8=VCC
}}
</small>
 
'''Analog Devices ADS9288 pinout''':
{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!AD9288 pins
!Description
 
|-
| S1, S2
| S1 depends on FX2 PA7 (see below), S2 is tied to GND.
|-
| DFS
| Tied to GND. Data format select = "offset binary" (not "twos complement").
|-
| A<sub>IN</sub>A, A<sub>IN</sub>B
| Analog input channels.
 
|}
 
'''Cypress FX2 pinout''':
{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!FX2&nbsp;pins
!Description
 
|-
| CTL0
| Connected to AD9288 ENC<sub>A</sub> and ENC<sub>B</sub> and FX2 IFCLK.
|-
| PB0-PB7
| Connected to AD9288 D0<sub>A</sub>-D7<sub>A</sub> and SN74LVC16245A 1A1-1A8.
|-
| PD0-PD7
| Connected to AD9288 D0<sub>B</sub>-D7<sub>B</sub> and SN74LVC16245A 2A1-2A8.
|-
| PA7
| Connected to the SN74LVC16245A's 1OE# and 2OE# pins (both 8bit groups share the signal) as well as 1DIR and 2DIR. Also connected to the ADC's S1 pin (via two discrete inverters with R37, Q2, R13, Q1).
 
This means PA7 selects between digital (low) and analog (high) data paths, data is always at FX2 ports PB and PD, and either carries 16 digital channels, or two eight bit analog channels.
 
The benefit of "variable DIR" in the SN74LVC16245A is questionable, since it shares the signal with OE# and for high levels the output is high-Z anyway -- so the ADC output is ''not'' routed to digital pins when PA7 is high, not tying DIR to a fixed level is pointless(?)
 
{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!PA7
!Description
|-
| 1 || Selects scope mode. The ADC's S1 pin is high, which means "Normal operation, data align disabled". The SN74LVC16245A's OE# pins are high ("don't enable output", DIR state is irrelevant).
|-
| 0 || Selects LA mode. The ADC's S1 pin is low, which means "Standby both channels A and B". The SN74LVC16245A's OE# pins are low ("output enable") and the DIR pins are low ("B data to A bus", i.e. data direction is from LA connector to FX2).
|}
 
|-
| PC2
| 1kHz probe calibration pin.
|-
| PC0/PC1
| Dual-color (red/green) LED.
 
{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!PC1
!PC0
!LED
|-
| 0 || 0 || ?
|-
| 0 || 1 || green
|-
| 1 || 0 || red
|-
| 1 || 1 || off
|}
 
|}


== Photos ==
== Photos ==
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File:Hantek 6022bl s1661sz b212fg.jpg|<small></small>
File:Hantek 6022bl s1661sz b212fg.jpg|<small></small>
File:Hantek 6022bl mornsun a0505s-2wr2.jpg|<small></small>
File:Hantek 6022bl mornsun a0505s-2wr2.jpg|<small></small>
File:Hantek_6022BL_PCB.jpg|<small></small>
File:Hantek6022BL-CPU.jpg|<small></small>
</gallery>
</gallery>


Line 111: Line 252:


* [http://1drv.ms/1gWOsUF Vendor software and manuals]
* [http://1drv.ms/1gWOsUF Vendor software and manuals]
* [http://geek-mag.com/posts/255290/ geek-mag.com: The overview of an USB oscillograph Hantek DSO-6022BL with the logical analyzer and gikporny]


[[Category:Device]]
[[Category:Device]]

Latest revision as of 18:32, 18 December 2021

Hantek 6022BL
Hantek 6022be mugshot.png
Status supported
Source code hantek-6xxx
Channels 2
Samplerate 48MHz
Analog bandwidth 20MHz
Vertical resolution 8bit
Triggers none (SW-only)
Input impedance 1MΩ‖25pF
Memory none
Display none
Connectivity USB
Website hantek.com

The Hantek 6022BL is a USB-based, 2-channel oscilloscope with an analog bandwidth of 20MS/s and 48MS/s sampling rate, and an 8-/16-channel logic analyzer with 24MHz sampling rate.

The device can either be used as oscilloscope or as logic analyzer, but not both at the same time. I.e., it is not a mixed-signal-oscilloscope (MSO).

Currently only the 8-channel logic analyzer mode is supported.

See Hantek 6022BL/Info for more details (such as lsusb -v output) about the device.

Hardware

The device has a "H/P" button. Depending on whether or not it's pressed it comes up with different USB VID/PIDs:

NXP 74HC4051D (upper/lower, CH1/CH2) pinout:

Y4 1-   O -16 VCC
(GND) Y6 2- -15 Y2
(upper EL5166, IN-) Z 3- -14 Y1
(GND) Y7 4- -13 Y0
(GND) Y5 5- -12 Y3
(GND) E# 6- -11 S0 (FX2 PA1)
VEE 7- -10 S1 (FX2 PA2)
GND 8- -9 S2 (FX2 PA3)
(GND) Y4 1-   O -16 VCC
(GND) Y6 2- -15 Y2
(lower EL5166, IN-) Z 3- -14 Y1
(GND) Y7 4- -13 Y0
(GND) Y5 5- -12 Y3
(GND) E# 6- -11 S0 (FX2 PA4)
VEE 7- -10 S1 (FX2 PA5)
GND 8- -9 S2 (FX2 PA6)

S2 S1 S0 74HC4051D Mux VDIVs (vendor software)
0 0 0 Y0 to Z 200mV
0 0 1 Y1 to Z 500mV
0 1 0 Y2 to Z 5V, 2V, 1V
0 1 1 Y3 to Z 100mV, 50mV, 20mV

Intersil EL5166 (both) pinout:

NC 1-   O -8 CE#
(upper/lower 74HC4051D, Z) IN- 2- -7 VS+
(AD8065, IN-/VOUT) IN+ 3- -6 OUT
VS- 4- -5 NC

Microchip 24LC02BI (both) pinout:

(Low, but not GND) A0 1-   O -8 VCC
(GND) A1 2- -7 WP (GND)
(GND) A2 3- -6 SCL (FX2 SCL)
VSS 4- -5 SDA (FX2 SDA)

Analog Devices ADS9288 pinout:

AD9288 pins Description
S1, S2 S1 depends on FX2 PA7 (see below), S2 is tied to GND.
DFS Tied to GND. Data format select = "offset binary" (not "twos complement").
AINA, AINB Analog input channels.

Cypress FX2 pinout:

FX2 pins Description
CTL0 Connected to AD9288 ENCA and ENCB and FX2 IFCLK.
PB0-PB7 Connected to AD9288 D0A-D7A and SN74LVC16245A 1A1-1A8.
PD0-PD7 Connected to AD9288 D0B-D7B and SN74LVC16245A 2A1-2A8.
PA7 Connected to the SN74LVC16245A's 1OE# and 2OE# pins (both 8bit groups share the signal) as well as 1DIR and 2DIR. Also connected to the ADC's S1 pin (via two discrete inverters with R37, Q2, R13, Q1).

This means PA7 selects between digital (low) and analog (high) data paths, data is always at FX2 ports PB and PD, and either carries 16 digital channels, or two eight bit analog channels.

The benefit of "variable DIR" in the SN74LVC16245A is questionable, since it shares the signal with OE# and for high levels the output is high-Z anyway -- so the ADC output is not routed to digital pins when PA7 is high, not tying DIR to a fixed level is pointless(?)

PA7 Description
1 Selects scope mode. The ADC's S1 pin is high, which means "Normal operation, data align disabled". The SN74LVC16245A's OE# pins are high ("don't enable output", DIR state is irrelevant).
0 Selects LA mode. The ADC's S1 pin is low, which means "Standby both channels A and B". The SN74LVC16245A's OE# pins are low ("output enable") and the DIR pins are low ("B data to A bus", i.e. data direction is from LA connector to FX2).
PC2 1kHz probe calibration pin.
PC0/PC1 Dual-color (red/green) LED.
PC1 PC0 LED
0 0 ?
0 1 green
1 0 red
1 1 off

Photos

Protocol

See Hantek 6022BE#Protocol.

When the "H/P" button is not pressed, the device can be used as 8-channel 24MHz logic analyzer via fx2lafw out of the box (using the fx2lafw protocol).

Firmware

See Hantek 6022BE#Firmware.

Resources

Retrieved from "https://sigrok.org/w/index.php?title=Hantek_6022BL&oldid=16233"