Difference between revisions of "LabNation SmartScope"
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(add links to my progress so far) |
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* '''Single-pole normally-closed SOP OptoMOS relay''': [http://www.ixysic.com/Products/SSRFormB.htm Ixys CPC1125N] ([http://www.ixysic.com/home/pdfs.nsf/www/CPC1125N.pdf/$file/CPC1125N.pdf datasheet]) | * '''Single-pole normally-closed SOP OptoMOS relay''': [http://www.ixysic.com/Products/SSRFormB.htm Ixys CPC1125N] ([http://www.ixysic.com/home/pdfs.nsf/www/CPC1125N.pdf/$file/CPC1125N.pdf datasheet]) | ||
* '''250MHz, rail-to-rail I/O, CMOS dual opamp''': [http://www.ti.com/product/opa2354 Texas Instruments OPA2354] ([http://www.ti.com/lit/gpn/opa2354 datasheet]) | * '''250MHz, rail-to-rail I/O, CMOS dual opamp''': [http://www.ti.com/product/opa2354 Texas Instruments OPA2354] ([http://www.ti.com/lit/gpn/opa2354 datasheet]) | ||
* '''Quad buffer/line driver with | * '''Quad buffer/line driver with 3-state outputs''': [http://diodes.com/catalog/standard_logic_189/74lvc126a.html Diodes Incorporated 74LVC126A] ([http://diodes.com/datasheets/74LVC126A.pdf datasheet]) | ||
* 0480000 OCP1332 1725 | |||
* 4x CGA4V | |||
* S03A | |||
== Photos == | == Photos == | ||
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== Protocol == | == Protocol == | ||
== Progress == | |||
Detection and bitstream loading implemented in libsigrok driver. Scope init and acquisition WIP in python test code. | |||
See https://github.com/karlp/libsigrok/tree/devel/labnation | |||
== Resources == | == Resources == | ||
Latest revision as of 22:34, 14 January 2018
 | |
| Status | planned |
|---|---|
| Channels | 8 |
| Samplerate | 100MHz |
| Samplerate (state) | — |
| Triggers | low, high, rising, falling, edge |
| Min/max voltage | ? |
| Threshold voltage | Fixed: VIL=0.8V, VIH=2.0V |
| Memory | 4Msamples (8MByte SDRAM) |
| Compression | ? |
| Website | lab-nation.com |
The LabNation SmartScope is a USB-based mixed-signal oscilloscope (100 MS/s, 45MHz bandwidth), 8-channel logic analyzer (100MHz), arbitrary waveform generator / function generator.
See LabNation SmartScope/Info for some more details (such as lsusb -v output) on the device.
Hardware
- FPGA (3840 logic cells): Xilinx XC6SXL4 (datasheet)
- 64Mbit SDRAM: Alliance Memory AS4C4M16S (datasheet)
- Dual-channel, 8-bit, 100Msps ADC: Maxim MAX19506 (datasheet)
- 8-bit microcontroller with full-speed USB: Microchip PIC18F14K50 (datasheet)
- Single-pole normally-closed SOP OptoMOS relay: Ixys CPC1125N (datasheet)
- 250MHz, rail-to-rail I/O, CMOS dual opamp: Texas Instruments OPA2354 (datasheet)
- Quad buffer/line driver with 3-state outputs: Diodes Incorporated 74LVC126A (datasheet)
- 0480000 OCP1332 1725
- 4x CGA4V
- S03A
Photos
Package, top
Package, bottom
Package, contents
Cables and probes
P6060 probe
Device, top
Device, bottom
Probe connector
Misc connectors
PCB, top
PCB, bottom
Analog frontend
Xilinx XC6SLX4
Alliance AS4C4M16S
Maxim MAX19506
Microchip 18LF14K50
Ixys CPC1125N
74LVC126A
TI OPA2354
Protocol
Progress
Detection and bitstream loading implemented in libsigrok driver. Scope init and acquisition WIP in python test code. See https://github.com/karlp/libsigrok/tree/devel/labnation