Difference between revisions of "Sysclk LWLA1034"
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(Now supported!) |
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| image = [[File:Sysclk lwla1034 mugshot.png|180px]] | | image = [[File:Sysclk lwla1034 mugshot.png|180px]] | ||
| name = Sysclk LWLA1034 | | name = Sysclk LWLA1034 | ||
| status = | | status = supported | ||
| source_code_dir = | | source_code_dir = | ||
| channels = 34 | | channels = 34 | ||
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== Firmware == | == Firmware == | ||
* The FX2 firmware | * The FX2 firmware is loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up. | ||
* Endpoint 4 | * Endpoint 4 is used exclusively for loading a new bitstream into the FPGA. | ||
* Endpoint 2 is | * Endpoint 2 is used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6. | ||
Reverse engineering of the vendor protocol | Reverse engineering of the vendor's custom protocol has been completed. See [[Sysclk LWLA1034/Protocol]] for the documentation. | ||
== Resources == | == Resources == | ||
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[[Category:Device]] | [[Category:Device]] | ||
[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category: | [[Category:Supported]] | ||
Revision as of 20:42, 14 January 2014
 | |
| Status | supported |
|---|---|
| Channels | 34 |
| Samplerate | 125MHz (max) |
| Samplerate (state) | ? |
| Triggers | 34 + extern |
| Min/max voltage | 0-5V |
| Threshold voltage | ? |
| Memory | 256Kbit/channel |
| Compression | RLE |
| Website | taobao.com |
The Sysclk LWLA1034 is a USB-based, 34-channel logic analyzer with up to 125MHz sampling rate.
See Sysclk LWLA1034/Info for more details (such as lsusb -v output) about the device.
Hardware
- Altera EP2C5Q208C8N (Cyclone II) FPGA
- Cypress CY7C68013A-56 (FX2) USB interface chip
- Cypress 256k×36 SRAM (likely a CY7C1361C-133AXC or similar)
The not-installed 10-pin connector between the USB socket and the large capacitor seems to connect to the JTAG pins of the FPGA.
Photos
(Note: The yellow/greenish markings weren't there, they're added by the photographer)
PCB for another device:
PCB, top
PCB, bottom
PCB, close-up
Cypress FX2
SRAM (marking removed)
Software
Firmware
- The FX2 firmware is loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up.
- Endpoint 4 is used exclusively for loading a new bitstream into the FPGA.
- Endpoint 2 is used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6.
Reverse engineering of the vendor's custom protocol has been completed. See Sysclk LWLA1034/Protocol for the documentation.