Difference between revisions of "Sysclk LWLA1034"
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| source_code_dir = | | source_code_dir = | ||
| channels = 34 | | channels = 34 | ||
| samplerate = 125MHz | | samplerate = 125MHz (max) | ||
| samplerate_state = ? | | samplerate_state = ? | ||
| triggers = | | triggers = 34 + extern | ||
| voltages = | | voltages = 0-5V | ||
| threshold = ? | | threshold = ? | ||
| memory = 256Kbit/channel | | memory = 256Kbit/channel | ||
| compression = | | compression = RLE | ||
| website = [http://item.taobao.com/item.htm?id=19834430293 taobao.com] | | website = [http://item.taobao.com/item.htm?id=19834430293 taobao.com] | ||
}} | }} | ||
Revision as of 22:08, 4 January 2014
 | |
| Status | in progress |
|---|---|
| Channels | 34 |
| Samplerate | 125MHz (max) |
| Samplerate (state) | ? |
| Triggers | 34 + extern |
| Min/max voltage | 0-5V |
| Threshold voltage | ? |
| Memory | 256Kbit/channel |
| Compression | RLE |
| Website | taobao.com |
The Sysclk LWLA1034 is a USB-based, 34-channel logic analyzer with up to 125MHz sampling rate.
See Sysclk LWLA1034/Info for more details (such as lsusb -v output) about the device.
Hardware
- Altera EP2C5Q208C8N (Cyclone II) FPGA
- Cypress CY7C68013A-56 (FX2) USB interface chip
- Cypress 256k×36 SRAM (likely a CY7C1361C-133AXC or similar)
Photos
PCB, top
PCB, bottom
PCB, close-up
Cypress FX2
SRAM (marking removed)
The not-installed 10-pin connector between the USB socket and the large capacitor seems to connect to the JTAG pins of the FPGA.
Software
Firmware
- The FX2 firmware appears to be loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up.
- Endpoint 4 appears to be used exclusively for loading a new bitstream into the FPGA.
- Endpoint 2 is apparently used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6.
Reverse engineering of the vendor protocol is currently in progress. See Sysclk LWLA1034/Protocol for a documentation of the findings gathered so far.