Difference between revisions of "Saleae Logic"

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[[File:Saleae Logic.jpg|thumb|right|Saleae Logic]]
{{Infobox logic analyzer
| image            = [[File:Saleae Logic.png|180px]]
| name            = Saleae Logic
| status          = supported
| source_code_dir  = fx2lafw
| channels        = 8
| samplerate      = 24MHz
| samplerate_state = —
| triggers        = none (SW-only)
| voltages        = -0.5V — 5.25V
| threshold        = Fixed: VIH=2.0V—5.25V, VIL=-0.5V—0.8V
| memory          = none
| compression      = none
| website          = [http://www.saleae.com/logic/ saleae.com]
}}


The [http://www.saleae.com/logic/ Saleae Logic] is a low-cost logic analyzer. The unit itself is very small, and has a USB 2.0 port connecting it to a PC (and powering the unit) and a connector for the 8+1 probe set. It is built around a Cypress EZ-USB FX2LP microcontroller — an 8051-compatible chip with built-in USB 2.0 controller. It can sample 8 channels up to 24MHz and sells for $150.
The '''Saleae Logic''' is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate.


The Logic reports on the USB bus with vendor ID 0x0925, product ID 0x3881. It has no firmware on board; this must be uploaded when the unit is powered on. The standard procedure for the FX2LP chip is used for this. After the firmware is on board, the chip resets and announces itself on the USB bus with the same vendor and product IDs, but this time with only two endpoints: endpoint 1 (out) is used for sending commands to the logic analyzer, endpoint 2 (in) is for transfers of sample sets. Both endpoints are of type BULK.
The unit itself is very small, and has a USB 2.0 port connecting it to a PC (and powering the unit) and a connector for the 8 + 1 probe set. It is built around a Cypress EZ-USB FX2LP microcontroller — an 8051-compatible chip with built-in USB 2.0 controller. It can sample 8 channels up to 24MHz.


The Logic does no analysis in hardware at all. Processing triggers, protocol analysis and so on is all done on the software side; the hardware unit merely sends the requested number of samples at a given sample rate. The LA has 8 probes, all of which are always probed and sent along. A full sample is thus always exactly one byte.
In sigrok, we use the open-source [[fx2lafw]] firmware for this logic analyzer.


There is only one command the software sends to the Logic on endpoint 1: a two-byte command to set the sample rate. The first byte is always 0x01. This is likely a command opcode meaning "set sample rate".
See [[Saleae Logic/Info]] for more details (such as '''lsusb -vvv''' output) about the device.


The second byte indicates the sample rate. The rate is given in the form of a divider based on the FX2LP's clock, which runs at 48MHz. The following formula is used:
See [[Saleae Logic16]] for the successor product of the Saleae Logic.


rate = 48 / (1 + divider)
== Hardware ==


Thus a sample rate of 2 MHz is selected by using 23 as the divider. The following sample rates are supported:
* '''Main chip:''' Cypress CY7C68013A-56PVXC (FX2LP)
* '''ESD protection''': ST DVIULC6-4SC6
* '''3.3V voltage regulator''': ST LD33C
* '''I2C EEPROM''': Microchip 24LC00
* '''Crystal''': 24MHz


{| border="0" style="font-size: smaller"
The case has four '''Torx T2''' screws you need to remove in order to be able to open it.
|- bgcolor="#6699ff"
!Rate (Mhz)
!Divider
|- bgcolor="#eeeeee"
| 0.2
| 239
|- bgcolor="#dddddd"
| 0.25
| 191
|- bgcolor="#eeeeee"
| 0.5
| 95
|- bgcolor="#dddddd"
| 1
| 47
|- bgcolor="#eeeeee"
| 2
| 23
|- bgcolor="#dddddd"
| 4
| 11
|- bgcolor="#eeeeee"
| 8
| 5
|- bgcolor="#dddddd"
| 12
| 3
|- bgcolor="#eeeeee"
| 16
| 2
|- bgcolor="#dddddd"
| 24
| 1
|}


Samples are read off endpoint 2. the Logic receives a read request from the host, and responds by sending the requested number of samples. The maximum number of samples is 4096, a constraint in the USB protocol. A sample is one byte, with each bit representing the state of one of the probes. Probe 1 (black wire) is in the MSB of the sample, probe 8 (purple wire) is the LSB.
== Photos ==
 
<gallery>
File:Saleae Logic.jpg|<small>Device, top</small>
File:Saleae logic.jpg|<small>Device with two E-Z-Hooks</small>
File:Saleae logic opened.jpg|<small>Device, open</small>
File:Saleae logic pcb front.jpg|<small>PCB, front</small>
File:Saleae logic pcb back.jpg|<small>PCB, back</small>
File:Saleae logic collection.jpg|<small>Saleae Logic collection</small>
</gallery>
 
== Protocol ==
 
Since we use the open-source [[fx2lafw]] firmware for this device, we don't need to know the protocol.
 
However, for those interested in this, see our old [[Saleae_Logic/Info#Vendor_USB_protocol|vendor protocol docs]].
 
== Resources ==
 
* [http://downloads.saleae.com/Logic+Guide.pdf User's guide]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]
 
[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

Latest revision as of 12:07, 28 July 2013

Saleae Logic
Saleae Logic.png
Status supported
Source code fx2lafw
Channels 8
Samplerate 24MHz
Samplerate (state) —
Triggers none (SW-only)
Min/max voltage -0.5V — 5.25V
Threshold voltage Fixed: VIH=2.0V—5.25V, VIL=-0.5V—0.8V
Memory none
Compression none
Website saleae.com

The Saleae Logic is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate.

The unit itself is very small, and has a USB 2.0 port connecting it to a PC (and powering the unit) and a connector for the 8 + 1 probe set. It is built around a Cypress EZ-USB FX2LP microcontroller — an 8051-compatible chip with built-in USB 2.0 controller. It can sample 8 channels up to 24MHz.

In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.

See Saleae Logic/Info for more details (such as lsusb -vvv output) about the device.

See Saleae Logic16 for the successor product of the Saleae Logic.

Hardware

  • Main chip: Cypress CY7C68013A-56PVXC (FX2LP)
  • ESD protection: ST DVIULC6-4SC6
  • 3.3V voltage regulator: ST LD33C
  • I2C EEPROM: Microchip 24LC00
  • Crystal: 24MHz

The case has four Torx T2 screws you need to remove in order to be able to open it.

Photos

  • Device, top

  • Device with two E-Z-Hooks

  • Device, open

  • PCB, front

  • PCB, back

  • Saleae Logic collection

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

However, for those interested in this, see our old vendor protocol docs.

Resources

Retrieved from "https://sigrok.org/w/index.php?title=Saleae_Logic&oldid=6820"