Difference between revisions of "KingST KQS3506-LA16100"
Jump to navigation
Jump to search
Uwe Hermann (talk | contribs) (EEPROM pinout and connections.) |
Uwe Hermann (talk | contribs) (→Hardware: Start the CLPD pinout.) |
||
| Line 29: | Line 29: | ||
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet]) | * '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet]) | ||
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet]) | * '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet]) | ||
'''Pinouts and connections:''' | '''Pinouts and connections:''' | ||
'''I2C EEPROM:''' | '''I2C EEPROM:''' | ||
| Line 36: | Line 38: | ||
The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C EEPROM address of the EEPROM 0x50. | The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C EEPROM address of the EEPROM 0x50. | ||
{{chip_8pin|1=A0 <span style="color:green">(GND)</span>|2=A1 <span style="color:green">(GND)</span>|3= A2 <span style="color:green">(GND)</span>|4=GND|5=SDA <span style="color:green">(FX2 SDA)</span>|6=SCL <span style="color:green">(FX2 SCL)</span>|7=WP <span style="color:green">(jumper)</span>|8=VCC <span style="color:green">(3.3V)</span>}} | {{chip_8pin|1=A0 <span style="color:green">(GND)</span>|2=A1 <span style="color:green">(GND)</span>|3= A2 <span style="color:green">(GND)</span>|4=GND|5=SDA <span style="color:green">(FX2 SDA)</span>|6=SCL <span style="color:green">(FX2 SCL)</span>|7=WP <span style="color:green">(jumper W2)</span>|8=VCC <span style="color:green">(3.3V)</span>}} | ||
'''CLPD:''' | |||
The Altera EPM3032A JTAG pins are available on the '''J3''' pin header. | |||
{| border="0" style="font-size: smaller" class="sigroktable" | |||
|- | |||
!1 | |||
!2 | |||
!3 | |||
!4 | |||
!5 | |||
!6 | |||
!7 | |||
!8 | |||
!9 | |||
!10 | |||
!11 | |||
|- | |||
| JTAG TDI | |||
| | |||
| | |||
| GND | |||
| | |||
| | |||
| JTAG TMS | |||
| | |||
| VCC | |||
| | |||
| GND | |||
|- | |||
!12 | |||
!13 | |||
!14 | |||
!15 | |||
!16 | |||
!17 | |||
!18 | |||
!19 | |||
!20 | |||
!21 | |||
!22 | |||
|- | |||
| | |||
| | |||
| | |||
| | |||
| GND | |||
| VCC | |||
| | |||
| | |||
| | |||
| | |||
| | |||
|- | |||
!23 | |||
!24 | |||
!25 | |||
!26 | |||
!27 | |||
!28 | |||
!29 | |||
!30 | |||
!31 | |||
!32 | |||
!33 | |||
|- | |||
| | |||
| GND | |||
| | |||
| JTAG TCK | |||
| | |||
| | |||
| VCC | |||
| GND | |||
| | |||
| JTAG TDO | |||
| | |||
|- | |||
!34 | |||
!35 | |||
!36 | |||
!37 | |||
!38 | |||
!39 | |||
!40 | |||
!41 | |||
!42 | |||
!43 | |||
!44 | |||
|- | |||
| | |||
| | |||
| GND | |||
| | |||
| | |||
| | |||
| | |||
| VCC | |||
| | |||
| | |||
| | |||
|} | |||
== Photos == | == Photos == | ||
Revision as of 20:30, 25 July 2013
 | |
| Status | planned |
|---|---|
| Channels | 2/4/8/16 |
| Samplerate | 100/50/25/12.5MHz |
| Samplerate (state) | — |
| Triggers | none (SW-only) |
| Min/max voltage | -0.9V — 6V |
| Threshold voltage |
configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V |
| Memory | none |
| Compression | yes |
| Website | taobao.com |
The KingST KQS3506-LA16100 is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).
This is a clone of the Saleae Logic16.
See KingST KQS3506-LA16100/Info for more details (such as lsusb -vvv output) about the device.
Hardware
- FPGA: Xilinx Spartan-3A XC3S200A, 200K gates (datasheeet)
- CPLD: Altera EPM3032A, 600 gates, 32 macrocells (datasheet, pinout).
- USB interface chip: Cypress CY7C68013A-56PVXC (FX2LP) (datasheet)
- I2C EEPROM: Microchip 24LC02B (datasheet)
- 3.3V voltage regulator: Advanced Monolithic Systems AMS1117-3.3 (datasheet, older datasheet)
- 1.2V voltage regulator: Advanced Monolithic Systems AMS1117-1.2 (datasheet, older datasheet)
Pinouts and connections:
I2C EEPROM:
The Microchip 24LC02B is connected to the Cypress FX2. The WP pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C EEPROM address of the EEPROM 0x50.
| A0 (GND) | 1- | O | -8 | VCC (3.3V) |
| A1 (GND) | 2- | -7 | WP (jumper W2) | |
| A2 (GND) | 3- | -6 | SCL (FX2 SCL) | |
| GND | 4- | -5 | SDA (FX2 SDA) |
CLPD:
The Altera EPM3032A JTAG pins are available on the J3 pin header.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
|---|---|---|---|---|---|---|---|---|---|---|
| JTAG TDI | GND | JTAG TMS | VCC | GND | ||||||
| 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
| GND | VCC | |||||||||
| 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 |
| GND | JTAG TCK | VCC | GND | JTAG TDO | ||||||
| 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 |
| GND | VCC |
Photos
TODO.