Difference between revisions of "Main Page"
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== Design goals == | == Design goals == | ||
* ''' | * '''Broad hardware support'''. Supports a wide variety of logic analyzers from various vendors with different capabilities. | ||
* '''Cross-platform'''. Works on Linux, Mac OS X and Windows, and on architectures including x86, ARM, Sparc and PowerPC. | * '''Cross-platform'''. Works on [[Linux]], [[Mac OS X]] and [[Windows]], and on many architectures including x86, ARM, Sparc and PowerPC. | ||
* '''Scriptable'''. Extendable with protocol decoders and analyzers written in Python. | * '''Scriptable protocol decoding'''. Extendable with [[protocol decoders]] and analyzers written in Python. | ||
* '''Format support'''. Supports various input and output formats (raw, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], others). | * '''Format support'''. Supports various [[Input output formats|input and output formats]] (raw, ASCII, hex, CSV, gnuplot, [http://en.wikipedia.org/wiki/Value_change_dump VCD], others). | ||
== Supported hardware == | == Supported hardware == | ||
Revision as of 19:53, 8 April 2010
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The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL. Design goals
Supported hardware
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