Difference between revisions of "Kingst LA2016/Info"

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   (Bus Powered)
   (Bus Powered)
</small>
</small>
== Observations of the LA2016 Internal SPI Bus ==
<small>
The software on the host PC controls the logic analyser capture settings by writing to a set of byte-wide control registers within the FPGA.<br />
It contains around 60 registers which are accessed using the SPI bus between the FX2 MCU and the FPGA (see schematic on sigrok wiki page).<br />
The SPI bus is configured with the FX2 as master and FPGA as slave. Every SPI transaction is two bytes and is framed by SPI CS (active low).<br />
The first byte contains the register address and a READ/write bit. The second byte contains the data, which is either written to the<br />
FPGA or read from it. Note that these transactions are all least significant bit first on the SPI bus, so your LA will need to<br />
reverse the bit order to interpret correctly.<br />
<br />
Capture status can be read from register address 0x00 and 0x01. After a capture has completed, information about the data location in SDRAM can<br />
be read from addresses 0x10-0x1B. For other registers, reading is not implemented and they just read as 0xFF. Where reading is implemented, the<br />
same address is used to access different registers based on read/write. For example, FPGA status is read from address 0x00 and 0x01 but writing 0x03<br />
to address 0x00 starts an acquistion.<br />
<br />
The FX2 MCU is simply acting as a 'dumb' gateway, translating USB requests for FPGA access into SPI bus requests. USB control OUT vendor class<br />
transfers with bRequest of 0x20 will write to the FPGA registers, whereas IN transfers will read them. For example, a USB request to read two<br />
bytes starting from address 0x00 would cause the FX2 to issue a SPI read for address 0x00 and then a read for address 0x01.<br />
<br />
=== SPI bus activity during OEM software initialisation ===
    First byte is FPGA register address. The MSbit is set for READ transfers.
    |
    |  Second byte is data being written or read
    |  |
    |  |
    80 FF  <-- Read RUN STATUS
    81 FF
   
    80 FF  <-- Read RUN STATUS
    81 FF
   
    68 3F  <-- Write SET INPUT THRESHOLD 
    69 02
    6A F2
    6B 00
   
    02 00  <-- Halt USER PWM outputs to begin settings change
   
    70 40  <-- USER PWM1 SETTINGS
    71 0D
    72 03
    73 00
    74 A0
    75 86
    76 01
    77 00
   
    78 D0  <-- USER PWM2 SETTINGS
    79 07
    7A 00
    7B 00
    7C E8
    7D 03
    7E 00
    7F 00
   
    02 03  <-- enable USER PWM outputs
=== SPI bus activity during capture sequence ===
OEM software with no triggers set does this to FPGA regs:
    First byte is FPGA register address. The MSbit is set for READ transfers.
    |
    |  Second byte is data being written or read
    |  |
    |  |
    03 00  <-- Set capture mode to be "write to SDRAM", rather than stream mode (where reg 03 = 01)
   
    TRIGGER SETUP
    20 FF  <-- enable all 16 channels (change on any channel will cause new repetition packet)
    21 FF
    22 00  <-- no triggers active
    23 00
    24 00
    25 00
    26 00
    27 00
    28 00
    29 00
    2A 00
    2B 00
    2C 00
    2D 00
    2E 00
    2F 00
   
    SAMPLING SETUP
    10 40  <-- 32 bit total samples count request
    11 42
    12 0F
    13 00
    14 00  <-- always zero
    15 00  <-- 32 bit pre-trigger samples
    16 00
    17 00
    18 00
    19 00  <- always zero
    1A 00    <--|
    1B 00    <--These 3 bytes are pre_trigger_mem_bytes, see set_sample_config()
    1C 04    <--|
    1D C8  <-- Capture rate  1D is divisor LSbyte  200MHz / divisor - sample rate
    1E 00  <--                1E is divisor MSbyte
    1F 00
   
   
    00 03  <--- RUN now running the capture
   
   
    80 E2  Reading capture status every 100ms or so from register address 0x00 and 0x01
    81 85  The run_state values in order are:
            0x85E2: Pre-sampling (for samples before trigger position, e.g. half of samples when set at 50% capture ratio)
            0x85EA: Waiting for trigger
            0x85EE: Running
            0x85ED: Done
   
    80 EE 
    81 85 
   
    80 EE
    81 85 
   
    80 ED
    81 85
   
   
   
   
    Read 12 bytes from the FPGA registers starting at address 0x10 FPGA_REG_CTRL_BULK to get:
            32bit n_rep_packets
            32bit n_rep_packets_before_trigger
            32bit write_pos   
    90 xx
    91 xx
    92 xx
    93 xx
    94 xx    see capture_info() driver function
    95 xx   
    96 xx    xx == value depends on capture data
    97 xx
    98 xx
    99 xx
    9A xx
    9B xx
   
   
    FPGA_REG_UPLOAD  Write two 32 bit numbers, SDRAM start address and n bytes for bulk upload
    08 00
    09 00
    0A 00
    0B 00    values written are derived from the above info on capture data
    0C 20
    0D A9
    0E 61
    0F 00
   
   
    01 01  Write to start the transfer of capture data from SDRAM to FX2 fifos (issued by FX2 when it receives USB command 0x38 START BULK TRANSFER)
   
          3ms gap
   
    00 00  HALT capture engine
</small>


__FORCETOC__
__FORCETOC__

Revision as of 11:42, 2 April 2021

lsusb (before firmware upload)

$ lsusb -v
Bus 002 Device 008: ID 77a1:01a2
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass          255 Vendor Specific Class
  bDeviceSubClass       255 Vendor Specific Subclass
  bDeviceProtocol       255 Vendor Specific Protocol
  bMaxPacketSize0        64
  idVendor           0x77a1 
  idProduct          0x01a2 
  bcdDevice            0.00
  iManufacturer           0 
  iProduct                0 
  iSerial                 0 
  bNumConfigurations      1
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength          171
    bNumInterfaces          1
    bConfigurationValue     1
    iConfiguration          0 
    bmAttributes         0x80
      (Bus Powered)
    MaxPower              100mA
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass    255 Vendor Specific Subclass
      bInterfaceProtocol    255 Vendor Specific Protocol
      iInterface              0 
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       1
      bNumEndpoints           6
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass    255 Vendor Specific Subclass
      bInterfaceProtocol    255 Vendor Specific Protocol
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x02  EP 2 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x88  EP 8 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       2
      bNumEndpoints           6
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass    255 Vendor Specific Subclass
      bInterfaceProtocol    255 Vendor Specific Protocol
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x02  EP 2 OUT
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x88  EP 8 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       3
      bNumEndpoints           6
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass    255 Vendor Specific Subclass
      bInterfaceProtocol    255 Vendor Specific Protocol
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0040  1x 64 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x02  EP 2 OUT
        bmAttributes            1
          Transfer Type            Isochronous
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            1
          Transfer Type            Isochronous
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               1
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x88  EP 8 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
Device Qualifier (for other device speed):
  bLength                10
  bDescriptorType         6
  bcdUSB               2.00
  bDeviceClass          255 Vendor Specific Class
  bDeviceSubClass       255 Vendor Specific Subclass
  bDeviceProtocol       255 Vendor Specific Protocol
  bMaxPacketSize0        64
  bNumConfigurations      1
Device Status:     0x0000
  (Bus Powered)

lsusb (after firmware upload)

$ lsusb -v
Bus 001 Device 022: ID 77a1:01a2 Kingst Kingst Logic Analyzer
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass            0 
  bDeviceSubClass         0 
  bDeviceProtocol         0 
  bMaxPacketSize0        64
  idVendor           0x77a1 
  idProduct          0x01a2 
  bcdDevice            0.00
  iManufacturer           1 Kingst
  iProduct                2 Kingst Logic Analyzer
  iSerial                 0 
  bNumConfigurations      1
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength       0x0020
    bNumInterfaces          1
    bConfigurationValue     1
    iConfiguration          0 
    bmAttributes         0x80
      (Bus Powered)
    MaxPower              100mA
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           2
      bInterfaceClass       255 Vendor Specific Class
      bInterfaceSubClass      0 
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x02  EP 2 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
Device Qualifier (for other device speed):
  bLength                10
  bDescriptorType         6
  bcdUSB               2.00
  bDeviceClass            0 
  bDeviceSubClass         0 
  bDeviceProtocol         0 
  bMaxPacketSize0        64
  bNumConfigurations      1
Device Status:     0x0000
  (Bus Powered)

Observations of the LA2016 Internal SPI Bus

The software on the host PC controls the logic analyser capture settings by writing to a set of byte-wide control registers within the FPGA.
It contains around 60 registers which are accessed using the SPI bus between the FX2 MCU and the FPGA (see schematic on sigrok wiki page).
The SPI bus is configured with the FX2 as master and FPGA as slave. Every SPI transaction is two bytes and is framed by SPI CS (active low).
The first byte contains the register address and a READ/write bit. The second byte contains the data, which is either written to the
FPGA or read from it. Note that these transactions are all least significant bit first on the SPI bus, so your LA will need to
reverse the bit order to interpret correctly.

Capture status can be read from register address 0x00 and 0x01. After a capture has completed, information about the data location in SDRAM can
be read from addresses 0x10-0x1B. For other registers, reading is not implemented and they just read as 0xFF. Where reading is implemented, the
same address is used to access different registers based on read/write. For example, FPGA status is read from address 0x00 and 0x01 but writing 0x03
to address 0x00 starts an acquistion.

The FX2 MCU is simply acting as a 'dumb' gateway, translating USB requests for FPGA access into SPI bus requests. USB control OUT vendor class
transfers with bRequest of 0x20 will write to the FPGA registers, whereas IN transfers will read them. For example, a USB request to read two
bytes starting from address 0x00 would cause the FX2 to issue a SPI read for address 0x00 and then a read for address 0x01.

SPI bus activity during OEM software initialisation

   First byte is FPGA register address. The MSbit is set for READ transfers.
   |
   |  Second byte is data being written or read
   |  |
   |  |
   80 FF   <-- Read RUN STATUS
   81 FF
   
   80 FF   <-- Read RUN STATUS
   81 FF
   
   68 3F   <-- Write SET INPUT THRESHOLD  
   69 02
   6A F2
   6B 00
   
   02 00  <-- Halt USER PWM outputs to begin settings change
   
   70 40  <-- USER PWM1 SETTINGS
   71 0D
   72 03
   73 00
   74 A0
   75 86
   76 01
   77 00
   
   78 D0  <-- USER PWM2 SETTINGS
   79 07
   7A 00
   7B 00
   7C E8
   7D 03
   7E 00
   7F 00
   
   02 03  <-- enable USER PWM outputs



SPI bus activity during capture sequence

OEM software with no triggers set does this to FPGA regs: 


   First byte is FPGA register address. The MSbit is set for READ transfers.
   |
   |  Second byte is data being written or read
   |  |
   |  |
   03 00  <-- Set capture mode to be "write to SDRAM", rather than stream mode (where reg 03 = 01)
   
   TRIGGER SETUP
   20 FF  <-- enable all 16 channels (change on any channel will cause new repetition packet)
   21 FF
   22 00  <-- no triggers active
   23 00
   24 00
   25 00
   26 00
   27 00
   28 00
   29 00
   2A 00
   2B 00
   2C 00
   2D 00
   2E 00
   2F 00
   
   SAMPLING SETUP
   10 40  <-- 32 bit total samples count request
   11 42
   12 0F
   13 00
   14 00  <-- always zero
   15 00  <-- 32 bit pre-trigger samples
   16 00
   17 00
   18 00
   19 00   <- always zero
   1A 00    <--|
   1B 00    <--These 3 bytes are pre_trigger_mem_bytes, see set_sample_config()
   1C 04    <--|
   1D C8  <-- Capture rate   1D is divisor LSbyte   200MHz / divisor - sample rate
   1E 00  <--                1E is divisor MSbyte
   1F 00
   
   
   00 03   <--- RUN now running the capture
   
   
   80 E2  Reading capture status every 100ms or so from register address 0x00 and 0x01
   81 85  The run_state values in order are:
           0x85E2: Pre-sampling (for samples before trigger position, e.g. half of samples when set at 50% capture ratio)
           0x85EA: Waiting for trigger
           0x85EE: Running
           0x85ED: Done
   
   80 EE  
   81 85  
   
   80 EE
   81 85  
   
   80 ED
   81 85
   
   
   
   
   Read 12 bytes from the FPGA registers starting at address 0x10 FPGA_REG_CTRL_BULK to get:
           32bit n_rep_packets
           32bit n_rep_packets_before_trigger
           32bit write_pos     
   90 xx
   91 xx
   92 xx
   93 xx
   94 xx     see capture_info() driver function
   95 xx    
   96 xx     xx == value depends on capture data
   97 xx
   98 xx
   99 xx
   9A xx
   9B xx
   
   
   FPGA_REG_UPLOAD  Write two 32 bit numbers, SDRAM start address and n bytes for bulk upload
   08 00
   09 00
   0A 00
   0B 00    values written are derived from the above info on capture data
   0C 20
   0D A9
   0E 61
   0F 00
   
   
   01 01  Write to start the transfer of capture data from SDRAM to FX2 fifos (issued by FX2 when it receives USB command 0x38 START BULK TRANSFER)
   
          3ms gap
   
   00 00  HALT capture engine


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