Difference between revisions of "Sysclk SLA5032"
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Uwe Hermann (talk | contribs) (Set status to Planned.) |
(Updated info about triggers, input impedance, voltages, threshold, compression, website) |
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| Line 6: | Line 6: | ||
| channels = 32 | | channels = 32 | ||
| samplerate = 500MHz | | samplerate = 500MHz | ||
| samplerate_state = | | samplerate_state = — | ||
| triggers = | | triggers = 32 | ||
| voltages = | | input_impedance = 200kΩ‖15pF | ||
| threshold = | | voltages = -50V..+50V | ||
| threshold = Logic 1 >=1.6V, Logic 0 <= 1.3V | |||
| memory = 2x 1Gbit DDR2 SDRAM | | memory = 2x 1Gbit DDR2 SDRAM | ||
| compression = | | compression = RLE | ||
| website = [ | | website = [https://sysclk.taobao.com/ sysclk.taobao.com] | ||
}} | }} | ||
Revision as of 13:20, 22 April 2019
 | |
| Status | planned |
|---|---|
| Channels | 32 |
| Samplerate | 500MHz |
| Samplerate (state) | — |
| Triggers | 32 |
| Min/max voltage | -50V..+50V |
| Threshold voltage | Logic 1 >=1.6V, Logic 0 <= 1.3V |
| Memory | 2x 1Gbit DDR2 SDRAM |
| Compression | RLE |
| Website | sysclk.taobao.com |
The Sysclk SLA5032 is a USB-based, 32-channel logic analyzer with up to 500MHz sampling rate.
See Sysclk SLA5032/Info for more details (such as lsusb -v output) about the device.
Hardware
Main board:
- Microcontroller: Atmel Atmega8A (datasheet)
- USB interface chip: Cypress CY7C68013A-56LTXI (FX2LP) (datasheet)
- 32Kbyte I²C EEPROM: Atmel 24C256N (datasheet)
- 256byte I²C EEPROM: Atmel 24C02N (datasheet)
- 8MByte SPI NOR flash: Macronix MX25L6445E (datasheet)
- 3.3V voltage regulator: Advanced Monolithic Systems AMS1117-3.3 (datasheet, older datasheet)
- DC-DC buck regulator: 4x Alpha and Omega AOZ1021AI (datasheet)
- Crystal: 24MHz
SODIMM daughterboard:
- FPGA: Xilinx Spartan XC6SLX16 (datasheet)
- 8MByte SPI NOR flash: Macronix MX25L6445E (datasheet)
- 1Gbit DDR2 SDRAM: 2x Micron MT47H64M16HR-25E:H (markings: "5DHI7 D9LHT") (datasheet)
- Crystal: 100MHz
