Difference between revisions of "KingST KQS3506-LA16100"

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| image            = [[File:Kingst kqs3506 la16100.png|180px]]
| image            = [[File:Kingst kqs3506 la16100.png|180px]]
| name            = KingST KQS3506-LA16100
| name            = KingST KQS3506-LA16100
| status          = planned
| status          = supported
| source_code_dir  =  
| source_code_dir  = saleae-logic16
| channels        = 2/4/8/16
| channels        = 3/6/9/16
| samplerate      = 100/50/25/12.5MHz
| samplerate      = 100/50/32/16MHz
| samplerate_state = —
| samplerate_state = —
| triggers        = none (SW-only)
| triggers        = none (SW-only)
| voltages        = -0.9V — 6V
| voltages        = -0.9V — 6V
| threshold        = configurable:<br />for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V<br />for 5V systems: VIH=3.6V, VIL=1.4V
| threshold        = configurable:<br />for 1.8V to 3.6V systems: V<sub>IH</sub>=1.4V, V<sub>IL</sub>=0.7V<br />for 5V systems: V<sub>IH</sub>=3.6V, V<sub>IL</sub>=1.4V
| memory          = none
| memory          = none
| compression      = yes
| compression      = yes
Line 15: Line 15:
}}
}}


The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).  
The '''KingST KQS3506-LA16100''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).


This is a clone of the [[Saleae Logic16]].
This is a clone of the [[Saleae Logic16]].


See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -vvv''' output) about the device.
See [[KingST KQS3506-LA16100/Info]] for more details (such as '''lsusb -v''' output) about the device.


== Hardware ==
== Hardware ==


* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheet])
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''CPLD''': [http://www.altera.com/literature/lit-m3k.jsp Altera EPM3032A], 600 gates, 32 macrocells ([http://www.altera.com/literature/ds/m3000a.pdf datasheet], [http://www.altera.com/literature/dp/max3k/epm3032a.pdf pinout]).
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
Line 29: Line 29:
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''3.3V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-3.3] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
* '''1.2V voltage regulator''': [http://www.advanced-monolithic.com/products/voltreg.html#1117 Advanced Monolithic Systems AMS1117-1.2] ([http://ams-semitech.com/attachments/File/AMS1117_20120314.pdf datasheet], [http://www.advanced-monolithic.com/pdf/ds1117.pdf older datasheet])
 
* '''Crystal''': 24.000


'''Pinouts and connections:'''
'''Pinouts and connections:'''
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The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.
The Microchip 24LC02B is connected to the Cypress FX2. The '''WP''' pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.


{{chip_8pin|1=A0 <span style="color:green">(GND)</span>|2=A1 <span style="color:green">(GND)</span>|3= A2 <span style="color:green">(GND)</span>|4=GND|5=SDA <span style="color:green">(FX2 SDA)</span>|6=SCL <span style="color:green">(FX2 SCL)</span>|7=WP <span style="color:green">(jumper W2)</span>|8=VCC <span style="color:green">(3.3V)</span>}}
<small>
{{chip_8pin
| 1=<span style="color:green">(GND)</span> A0
| 2=<span style="color:green">(GND)</span> A1
| 3=<span style="color:green">(GND)</span> A2
| 4=GND
| 5=SDA <span style="color:green">(FX2 SDA)</span>
| 6=SCL <span style="color:green">(FX2 SCL)</span>
| 7=WP <span style="color:green">(jumper W2)</span>
| 8=VCC <span style="color:green">(3.3V)</span>
}}
</small>


'''CLPD:'''
'''CLPD:'''
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== Photos ==
== Photos ==


TODO.
'''Revision 5.0''':
 
<gallery>
File:Kingst kqs3506 la16100 package.jpg|<small>Package</small>
File:Kingst kqs3506 la16100 paper.jpg|<small>Paper</small>
File:Kingst kqs3506 la16100 device top.jpg|<small>Device, top</small>
File:Kingst kqs3506 la16100 device bottom.jpg|<small>Device, bottom</small>
File:Kingst kqs3506 la16100 device usb.jpg|<small>Device, USB</small>
File:Kingst kqs3506 la16100 device connector.jpg|<small>Device, connector</small>
File:Kingst kqs3506 la16100 pcb top.jpg|<small>PCB, top</small>
File:Kingst kqs3506 la16100 pcb bottom.jpg|<small>PCB, bottom</small>
File:Kingst kqs3506 la16100 xilinx spartan xc3s200a.jpg|<small>Xilinx XC3S200A</small>
File:Kingst kqs3506 la16100 altera epm3032a.jpg|<small>Altera EPM3032A</small>
File:Kingst kqs3506 la16100 cypress fx2.jpg|<small>Cypress FX2</small>
File:Kingst kqs3506 la16100 at88sc0104 silkscreen.jpg|<small>AT88SC0104 silkscreen</small>
File:Kingst kqs3506 la16100 microchip 24lc02b.jpg|<small>Microchip 24LC02B</small>
File:Kingst kqs3506 la16100 inputstage 2.jpg|<small>Input stage, 1</small>
File:Kingst kqs3506 la16100 input stage1.jpg|<small>Input stage, 2</small>
File:Kingst kqs3506 la16100 ams1117 33.jpg|<small>AMS1117-3.3</small>
File:Kingst kqs3506 la16100 ams1117 12.jpg|<small>AMS1117-1.2</small>
</gallery>
 
'''Revision 6.0''':
 
<gallery>
File:Kingst kqs3506 la16100 pcb v6 top.jpg|<small>PCB, top</small>
File:Kingst kqs3506 la16100 pcb v6 bottom.jpg|<small>PCB, bottom</small>
File:Kingst kqs3506 la16100 schematic v6.png|<small>Schematic drawn from PCB</small>
</gallery>
 
== Firmware ==
 
See [[Saleae_Logic16#Firmware]].


== Protocol ==
== Protocol ==
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[[Category:Device]]
[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Logic analyzer]]
[[Category:Planned]]
[[Category:Supported]]

Latest revision as of 22:09, 2 April 2019

KingST KQS3506-LA16100
Kingst kqs3506 la16100.png
Status supported
Source code saleae-logic16
Channels 3/6/9/16
Samplerate 100/50/32/16MHz
Samplerate (state) —
Triggers none (SW-only)
Min/max voltage -0.9V — 6V
Threshold voltage configurable:
for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V
for 5V systems: VIH=3.6V, VIL=1.4V
Memory none
Compression yes
Website taobao.com

The KingST KQS3506-LA16100 is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

This is a clone of the Saleae Logic16.

See KingST KQS3506-LA16100/Info for more details (such as lsusb -v output) about the device.

Hardware

Pinouts and connections:

I2C EEPROM:

The Microchip 24LC02B is connected to the Cypress FX2. The WP pin of the EEPROM can be jumpered to low or high, in order to write-protect it (or not). The address pins (A0-A2) are all connected to GND, which makes the I2C slave address of the EEPROM 0x50.

(GND) A0 1-   O -8 VCC (3.3V)
(GND) A1 2- -7 WP (jumper W2)
(GND) A2 3- -6 SCL (FX2 SCL)
GND 4- -5 SDA (FX2 SDA)

CLPD:

The Altera EPM3032A JTAG pins are available on the J3 pin header.

1 2 3 4 5 6 7 8 9 10 11
JTAG TDI I/O (FX2 PA7) I/O (FX2 PA6) GND I/O (FX2 PA5) I/O (FX2 PA4) JTAG TMS I/O (FX2 PA3) VCC I/O (FX2 PA2) GND
12 13 14 15 16 17 18 19 20 21 22
I/O (FX2 PA1) I/O (FX2 PA0) I/O (FPGA PROG_B) I/O (FPGA 94, IO_L05N_0) GND VCC I/O (FPGA 85, IO_L03P_0) I/O (FX2 CTL2) I/O (FX2 CTL1) I/O (FX2 CTL0) I/O (FPGA 51, DIN/MISO)
23 24 25 26 27 28 29 30 31 32 33
I/O (NC?) GND I/O (FPGA 97, IP0) JTAG TCK I/O (FPGA 53, CCLK) I/O (NC?) VCC GND I/O (FPGA 3, IO_L01P_3) JTAG TDO I/O (NC?)
34 35 36 37 38 39 40 41 42 43 44
I/O (NC?) I/O (NC?) GND I/O (NC?) I/O (NC?) I/O (NC?) I/O (NC?) VCC I/O (NC?) I/O (NC?) I/O (NC?)

JTAG header (CPLD):

The J3 pin header is a JTAG connector wired to the CPLD (it is not additionally wired to the FPGA in a JTAG chain). The pins are (from left to right):

1 2 3 4 5 6
TMS TDI TCK TDO GND 3.3V

Photos

Revision 5.0:

  • Package

  • Paper

  • Device, top

  • Device, bottom

  • Device, USB

  • Device, connector

  • PCB, top

  • PCB, bottom

  • Xilinx XC3S200A

  • Altera EPM3032A

  • Cypress FX2

  • AT88SC0104 silkscreen

  • Microchip 24LC02B

  • Input stage, 1

  • Input stage, 2

  • AMS1117-3.3

  • AMS1117-1.2

Revision 6.0:

  • PCB, top

  • PCB, bottom

  • Schematic drawn from PCB

Firmware

See Saleae_Logic16#Firmware.

Protocol

See Saleae_Logic16#Protocol.

Resources

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