Difference between revisions of "LeCroy LogicStudio"
m (Voltage thresholds can be configured from 0.0V to 7.0V) |
Uwe Hermann (talk | contribs) |
||
| Line 2: | Line 2: | ||
| image = [[File:Lecroy-logicstudio.jpg|180px]] | | image = [[File:Lecroy-logicstudio.jpg|180px]] | ||
| name = LeCroy LogicStudio | | name = LeCroy LogicStudio | ||
| status = | | status = in progress | ||
| source_code_dir = | | source_code_dir = | ||
| channels = 16 | | channels = 16 | ||
| samplerate = | | samplerate = 1GHz (@ 8ch), 500MHz (@ 16ch) | ||
| samplerate_state = — | | samplerate_state = — | ||
| triggers = high/low state, rising/falling/any edge, more | | triggers = high/low state, rising/falling/any edge, more | ||
| voltages = ? | | voltages = ? | ||
| threshold = 0.0V | | threshold = configurable: 0.0V — 7.0V | ||
| memory = 40 KB | | memory = 40 KB | ||
| compression = none | | compression = none | ||
| Line 15: | Line 15: | ||
}} | }} | ||
The '''LeCroy LogicStudio''' is | The '''LeCroy LogicStudio''' is a USB-based, 16-channel logic analyzer with 1GHz samplerate. | ||
When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI. | |||
See [[LeCroy LogicStudio/Info]] for more details (such as '''lsusb -v''' output) about the device. | |||
== Hardware == | == Hardware == | ||
* '''FPGA''': Xilinx Spartan-6 XC6SLX16 | * '''FPGA''': Xilinx Spartan-6 XC6SLX16 | ||
* '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A] | * '''USB interface''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A] | ||
| Line 24: | Line 29: | ||
== Photos == | == Photos == | ||
<gallery> | <gallery> | ||
File:Lecroy-logicstudio.jpg|<small> | File:Lecroy-logicstudio.jpg|<small>Device, top</small> | ||
File:Lecroy-logicstudio-pcb.jpg|<small>PCB, front</small> | File:Lecroy-logicstudio-pcb.jpg|<small>PCB, front</small> | ||
File:Lecroy-logicstudio-fpga.jpg|<small>FPGA</small> | File:Lecroy-logicstudio-fpga.jpg|<small>FPGA</small> | ||
| Line 31: | Line 37: | ||
</gallery> | </gallery> | ||
== Trigger Capabilities == | == Protocol == | ||
=== Trigger Capabilities === | |||
The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder. | The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder. | ||
| Line 50: | Line 58: | ||
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires. | Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires. | ||
== Internals == | === Internals === | ||
The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002. | The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002. | ||
| Line 56: | Line 64: | ||
The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled. | The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled. | ||
Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are | Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continuously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires ''and'' the requested number of post-trigger samples have been acquired. | ||
At that point, you may retrieve the ringbuffer's contents from the device. | At that point, you may retrieve the ringbuffer's contents from the device. | ||
== Firmware revisions == | === Firmware revisions === | ||
As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes: | As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes: | ||
| Line 67: | Line 75: | ||
The FX2LP firmware is 4250 bytes: | The FX2LP firmware is 4250 bytes: | ||
* md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f | * md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f | ||
== Resources == | |||
* [http://teledynelecroy.com/doc/docview.aspx?id=6378 Datasheet] | |||
* [http://teledynelecroy.com/doc/docview.aspx?id=7699 Manual] | |||
* [http://teledynelecroy.com/support/softwaredownload/logicstudio.aspx Vendor software] | |||
[[Category:Device]] | |||
[[Category:Logic analyzer]] | |||
[[Category:In progress]] | |||
Revision as of 01:02, 4 December 2015
 | |
| Status | in progress |
|---|---|
| Channels | 16 |
| Samplerate | 1GHz (@ 8ch), 500MHz (@ 16ch) |
| Samplerate (state) | — |
| Triggers | high/low state, rising/falling/any edge, more |
| Min/max voltage | ? |
| Threshold voltage | configurable: 0.0V — 7.0V |
| Memory | 40 KB |
| Compression | none |
| Website | teledynelecroy.com |
The LeCroy LogicStudio is a USB-based, 16-channel logic analyzer with 1GHz samplerate.
When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.
See LeCroy LogicStudio/Info for more details (such as lsusb -v output) about the device.
Hardware
- FPGA: Xilinx Spartan-6 XC6SLX16
- USB interface: Cypress CY7C68013A
- Crystal (FX2LP): 24.000MHz
- Crystal (FPGA): Unknown, xpress0?
Photos
Device, top
PCB, front
FPGA
FX2
Protocol
Trigger Capabilities
The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder. There are two logic trigger blocks A and B which can optionally be combined in the following ways:
- A AND B
- A OR B
- A THEN B
Each logic trigger block offers the following match criteria:
- Rising edge
- Falling edge
- Any edge
- Level 0 (including pulse width)
- Level 1 (ditto)
- Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).
Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed. Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fires.
Internals
The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.
The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command controls whether the lower or the upper channels are enabled.
Samples are stored in the device's 40 KB memory. That memory block is used as a ringbuffer; samples are continuously written to it (thus overwriting old data if necessary) until the user-programmed trigger fires and the requested number of post-trigger samples have been acquired. At that point, you may retrieve the ringbuffer's contents from the device.
Firmware revisions
As of October 2015, the latest released LeCroy LogicStudio software ships with FPGA bitstreams that are 464196 bytes and have the following hashes:
- md5(lecroy-logicstudio16-16.bitstream) = 1ab904704def72f18543d9d7aa929002
- md5(lecroy-logicstudio16-8.bitstream) = 5763c67cb762c85c8b1d09dc1f239acb
The FX2LP firmware is 4250 bytes:
- md5(lecroy-logicstudio16-fx2lp.fw) = 1638e2a5ef211c10f48405c1c16a057f