Difference between revisions of "MiniLA"
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Uwe Hermann (talk | contribs) (Created page with "{{Infobox logic analyzer | image = 180px | name = MiniLA | status = planned | source_code_dir = | channels ...") |
Uwe Hermann (talk | contribs) m |
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[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category:Planned]] | [[Category:Planned]] | ||
[[Category:Open source hardware]] | |||
Latest revision as of 15:34, 23 November 2014
 | |
| Status | planned |
|---|---|
| Channels | 32 |
| Samplerate | 100MHz |
| Samplerate (state) | ? |
| Triggers | low, high, rising, falling, don't care |
| Min/max voltage | ? |
| Threshold voltage | ? |
| Memory | 128Kb/channel |
| Compression | ? |
| Website | minila.sf.net |
The MiniLA is a parallel port based, 32-channel logic analyzer with up to 100MHz sampling rate.
It is an open-hardware / open-source design.
Hardware
TODO.
Photos
TODO.
Protocol
TODO.