+
+B. Logic analyzer setup
+-----------------------
+
+The logic analyzer used is a Saleae Logic clone (at 500kHz):
+
+ Probe DS1307 pin
+ -------------------------
+ D0 (CH1) SCL
+ D1 (CH2) SDA
+
+The sigrok 0.7.1 command line used:
+
+sigrok-cli --driver fx2lafw --channels D0=CLK,D1=DATA \
+ --config samplerate=500khz:captureratio=1 --samples 1000 \
+ --triggers CLK=1,DATA=f --output-file <filename>
+
+
+rtc_ds1307_500khz_sqw32khz_mode12h_pm.sr
+----------------------------------------
+
+The file provides reading of time keeping registers as well as control register
+of the RTC chip, which was setup to 12-hours mode, time with PM flag, and
+square wave frequency 32768 Hz before in order to demonstrate bugfixes
+in the following GitHub pull request for libsigrokdecode
+(merged as b3f6033022006c8f4ee88a70155f3571bee1a2ca):
+
+ https://github.com/sigrokproject/libsigrokdecode/pull/10
+