sockit_owm: Cosmetics, typos, formatting.

[sigrok-dumps.git] / onewire / sockit_owm / README

diff --git a/onewire/sockit_owm/README b/onewire/sockit_owm/README
index ec19be4338ab555f80b538f0d6fa27ae6d6c5b0d..c84e36411d7ec9f731be58eaaff8b4457bf51be4 100644 (file)
--- a/onewire/sockit_owm/README
+++ b/onewire/sockit_owm/README
@@ -1,15 +1,32 @@
-This directory contains waveforms created by accesing various onewire devices
+-------------------------------------------------------------------------------
+Onewire dumps, sockit_owm master
+-------------------------------------------------------------------------------
+
+This directory contains waveforms created by accessing various onewire devices
 using the 'sockit_owm' Verilog master. The master is used in a demo hardware
 (Terasic DE1 development board, and a Quartus/Qsys project) and software (also
-available as a Nios II project) implementation available at the next GIT repo.
+available as a Nios II project) implementation.
 
+Details:
 https://github.com/jeras/sockit_owm
 
 
-This dumps were created using sigrok with the following command:
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Saleae Logic (at 8MHz):
+
+  Probe       1-Wire pin
+  ----------------------
+  1 (black)   OWR
+
+
+Data
+----
 
-sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr
+The sigrok command line used was:
 
+  sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr
 
 This is the console output after running the demo: