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Commit | Line | Data |
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1 | ------------------------------------------------------------------------------- | |
2 | MAX6921 Shift Register | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a capture of data output to a Maxim MAX6921 high voltage shift | |
6 | register that was outputting data for a VFD clock. | |
7 | ||
8 | The signals were grabbed on a 28-pin PLCC chip (MAX6921) which outputs 20-bits | |
9 | that is crafted as a design for VFD applications. | |
10 | ||
11 | Details: | |
12 | - BeagleBoard.org vendor tree: https://github.com/beagleboard/kernel | |
13 | - Beagle Nixie GitHub: https://github.com/mranostay/beagle-nixie/ | |
14 | - MAX6921 datasheet: http://datasheets.maximintegrated.com/en/ds/MAX6921-MAX6931.pdf | |
15 | ||
16 | ||
17 | Logic analyzer setup | |
18 | -------------------- | |
19 | ||
20 | The logic analyzer used was Open Bench Logic Sniffer (at 10MHz): | |
21 | ||
22 | Probe MAX6921 pin | |
23 | -------------------------- | |
24 | 0 LOAD | |
25 | 1 DATA | |
26 | 2 CLK | |
27 | 3 BLANK (PWM Brightness Control) | |
28 | ||
29 | ||
30 | Data | |
31 | ---- | |
32 | ||
33 | The data contain various values for the VFD being driven, as reference at the | |
34 | prototype Nixie Cape for the Beaglebone. | |
35 | ||
36 | Digit Bit | |
37 | ----------------------- | |
38 | 0 (1 << 12) | |
39 | 1 (1 << 19) | |
40 | 2 (1 << 13) | |
41 | 3 (1 << 18) | |
42 | 4 (1 << 14) | |
43 | 5 (1 << 17) | |
44 | 6 (1 << 16) | |
45 | 7 (1 << 15) | |
46 | 8 (1 << 15) | |
47 | 9 (1 << 11) | |
48 | ||
49 | Segment Bit | |
50 | ----------------------- | |
51 | SEG_A (1 << 0) | |
52 | SEG_B (1 << 1) | |
53 | SEG_C (1 << 2) | |
54 | SEG_D (1 << 3) | |
55 | SEG_E (1 << 4) | |
56 | SEG_F (1 << 5) | |
57 | SEG_G (1 << 6) | |
58 | SEG_H (1 << 7) | |
59 | ||
60 | The sigrok command line used was: | |
61 | ||
62 | sigrok-cli --driver=ols:conn=/dev/ttyACM0 --config samplerate=10mhz \ | |
63 | --samples=24576 -p 0=LOAD,1=DATA,2=CLK,3=BLANK -o <filename> | |
64 |