[sigrok-dumps.git] / i2s / 2ch-32bit-8khz / README

-------------------------------------------------------------------------------
I2S Master 2-channel 32-bit 8-kHz
-------------------------------------------------------------------------------

This is an example of an I2S master playing a recording of the BBC
shipping forecast through one channel, and the other channel disconnected.


Logic analyzer setup
--------------------

The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):

  Probe       I2S pin
  -------------------
  0           Clock
  1           Frame Select
  2           Data
Commit	Line	Data
	1	-------------------------------------------------------------------------------
	2	I2S Master 2-channel 32-bit 8-kHz
	3	-------------------------------------------------------------------------------
	4
	5	This is an example of an I2S master playing a recording of the BBC
	6	shipping forecast through one channel, and the other channel disconnected.
	7
	8
	9	Logic analyzer setup
	10	--------------------
	11
	12	The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):
	13
	14	Probe I2S pin
	15	-------------------
	16	0 Clock
	17	1 Frame Select
	18	2 Data