projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 38019245 UH |
1 | ------------------------------------------------------------------------------- |
| 2 | SPI modes | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a set of example captures of some SPI transmissions with various | |
| 6 | SPI modes (CPOL/CPHA combinations), CS# polarity settings, word sizes, | |
| 7 | LSB-/MSB-first settings, and trigger setups. | |
| 8 | ||
| 9 | ||
| 10 | Logic analyzer setup | |
| 11 | -------------------- | |
| 12 | ||
| 13 | The logic analyzer used was a USBee SX (at 16MHz): | |
| 14 | ||
| 15 | Probe SPI | |
| 16 | --------------- | |
| 17 | 2 (red) MOSI | |
| 18 | 3 (orange) MISO | |
| 19 | 4 (yellow) CLK | |
| 20 | 5 (green) CS# | |
| 21 |