[sigrok-dumps.git] / lpc / vultureprog / README

-------------------------------------------------------------------------------
Arbitrary LPC (low pin count) traffic
-------------------------------------------------------------------------------

These captures are the identification and programming with random data of an
LPC (low pin count) interface flash chip. The LPC bus is emulated with an ARM
Cortex-M microcontroller, and does not run at the standard 33MHz clock.
Although the clock contains significant jitter, the connected chips respond
and communicate as expected.

Details:
http://en.wikipedia.org/wiki/Low_Pin_Count
http://www.intel.com/design/chipsets/industry/25128901.pdf


Hardware setup
--------------

A VultureProg daughterboard was attached to a TI Stellaris Launchpad board.
An SST49LF080A flash chip was installed in the PLCC socket. The core clock of
the CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to
capture all details of the waveform. The logic analyzer used was connected to
the "LPC probe" header of the VultureProg daughterboard.

Hardware: http://github.com/mrnuke/vultureprog-hardware
Firmware + SW: http://git.qiprog.org/

The logic analyzer used was an MCU123 USBee AX Pro clone (at 24MHz):

  Probe  LPC
  ----------
  0      LAD0
  1      LAD1
  2      LAD2
  3      LAD3
  4      LCLK
  5      LFRAME#


Data
----

lpc_vultureprog.sr:

  VultureProg BIOS chip programmer programming random data to an SST49LF080A.
  The bus clock was intentionally reduced to allow capture with an FX2-based
  logic analyzer.

The sigrok command line used was:

  sigrok-cli --driver fx2lafw --config samplerate=24mhz --samples 23552000 \
             -o <filename>

This data is released into the public domain.
Commit	Line	Data
e06e8eca AG	1	-------------------------------------------------------------------------------
	2	Arbitrary LPC (low pin count) traffic
	3	-------------------------------------------------------------------------------
	4
a661aa49 UH	5	These captures are the identification and programming with random data of an
	6	LPC (low pin count) interface flash chip. The LPC bus is emulated with an ARM
	7	Cortex-M microcontroller, and does not run at the standard 33MHz clock.
	8	Although the clock contains significant jitter, the connected chips respond
	9	and communicate as expected.
e06e8eca AG	10
	11	Details:
	12	http://en.wikipedia.org/wiki/Low_Pin_Count
	13	http://www.intel.com/design/chipsets/industry/25128901.pdf
	14
	15
a661aa49	16	Hardware setup
e06e8eca AG	17	--------------
e06e8eca AG	18
a661aa49 UH	19	A VultureProg daughterboard was attached to a TI Stellaris Launchpad board.
	20	An SST49LF080A flash chip was installed in the PLCC socket. The core clock of
	21	the CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to
	22	capture all details of the waveform. The logic analyzer used was connected to
	23	the "LPC probe" header of the VultureProg daughterboard.
e06e8eca AG	24
	25	Hardware: http://github.com/mrnuke/vultureprog-hardware
	26	Firmware + SW: http://git.qiprog.org/
	27
a661aa49 UH	28	The logic analyzer used was an MCU123 USBee AX Pro clone (at 24MHz):
	29
	30	Probe LPC
	31	----------
	32	0 LAD0
	33	1 LAD1
	34	2 LAD2
	35	3 LAD3
	36	4 LCLK
	37	5 LFRAME#
	38
e06e8eca AG	39
	40	Data
	41	----
	42
a661aa49 UH	43	lpc_vultureprog.sr:
	44
	45	VultureProg BIOS chip programmer programming random data to an SST49LF080A.
e06e8eca AG	46	The bus clock was intentionally reduced to allow capture with an FX2-based
	47	logic analyzer.
	48
a661aa49 UH	49	The sigrok command line used was:
	50
	51	sigrok-cli --driver fx2lafw --config samplerate=24mhz --samples 23552000 \
	52	-o <filename>
	53
e06e8eca	54	This data is released into the public domain.
a661aa49	55