projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 4c90e08e UH |
1 | ------------------------------------------------------------------------------- |
| 2 | EDID | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| fe2f7efc BV |
5 | The captures in this directory were taken from a VGA cable, connected to |
| 6 | various displays, as the EDID data was sent across the I2C bus. | |
| 7 | ||
| 8 | To decode these, set up a protocol decoder stack like this: | |
| 9 | ||
| 8266c455 | 10 | i2c -> i2cfilter -> edid |
| fe2f7efc | 11 | |
| 4c90e08e UH |
12 | Details: |
| 13 | https://en.wikipedia.org/wiki/Extended_display_identification_data | |
| 14 | https://en.wikipedia.org/wiki/Display_Data_Channel | |
| 15 | ||
| 16 | ||
| 17 | samsung_le46b620r3p.sr / samsung_syncmaster245b.sr | |
| 18 | -------------------------------------------------- | |
| 19 | ||
| 20 | The logic analyzer used was a Saleae Logic at 500kHz: | |
| 21 | ||
| 22 | Probe I2C pins | |
| 23 | -------------------- | |
| 24 | 1 (black) SDA | |
| 25 | 2 (brown) SCL | |
| 26 | ||
| 27 | ||
| 28 | samsung_syncmaster203b.sr | |
| 29 | ------------------------- | |
| 30 | ||
| 31 | The logic analyzer used was a Saleae Logic at 1MHz: | |
| 32 | ||
| 33 | Probe I2C pins | |
| 34 | -------------------- | |
| 35 | 1 (black) SCL | |
| 36 | 2 (brown) SDA | |
| 37 |