[sigrok-dumps.git] / aud / README

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Renesas/Hitachi AUD (Advanced User Debugger)
-------------------------------------------------------------------------------

This is a set of example captures of the Renesas/Hitachi AUD (Advanced User
Debugger) protocol.

Details:
http://www.renesas.eu/products/mpumcu/superh/sh7050/sh7058/Documentation.jsp
("rej09b0046 - SH7058 Hardware manual")


Logic analyzer setup
--------------------

  Probe       Pin
  ---------------
  1           AUDCK
  2           nAUDSYNC
  3           AUDATA3
  4           AUDATA2
  5           AUDATA1
  6           AUDATA0

The audgen-* files are artificially generated thus:

 - audgen-01.v is written in Verilog; due to limitations in sigrok only
   single-bit values are output.
 - Icarus Verilog is run to create a VCD dump:
   - "iverilog audgen-01.v"
   - "./a.out" (created by iverilog)
 - The resulting VCD can probably be opened directly by PulseView, but is
    here converted to a .sr dump.

AUD traffic can be challenging to capture because it is clocked out at the
MCU's clock frequency (20MHz typical). This requires an LA capable of either:

 - Timing analysis on 6 channels (clock, sync, data3..0) at >= 80MSps
   (40MSps gives very inconsistent results)
 - State analysis @ 20MHz, this would be "easy" but cheap hardware like
   Logic/Logic16 can't do it.


Data
----

Example to view decoded output:

  sigrok-cli -i audgen-01.sr -P aud:audck=AUDCK:naudsync=nAUDSYNC:audata3=AUDATA3:audata2=AUDATA2:audata1=AUDATA1:audata0=AUDATA0
Commit	Line	Data
84d7eaee	1	-------------------------------------------------------------------------------
	2	Renesas/Hitachi AUD (Advanced User Debugger)
	3	-------------------------------------------------------------------------------
	4
	5	This is a set of example captures of the Renesas/Hitachi AUD (Advanced User
	6	Debugger) protocol.
	7
	8	Details:
	9	http://www.renesas.eu/products/mpumcu/superh/sh7050/sh7058/Documentation.jsp
	10	("rej09b0046 - SH7058 Hardware manual")
	11
	12
	13	Logic analyzer setup
	14	--------------------
	15
	16	Probe Pin
	17	---------------
	18	1 AUDCK
	19	2 nAUDSYNC
	20	3 AUDATA3
	21	4 AUDATA2
	22	5 AUDATA1
	23	6 AUDATA0
	24
	25	The audgen-* files are artificially generated thus:
	26
	27	- audgen-01.v is written in Verilog; due to limitations in sigrok only
	28	single-bit values are output.
	29	- Icarus Verilog is run to create a VCD dump:
	30	- "iverilog audgen-01.v"
	31	- "./a.out" (created by iverilog)
	32	- The resulting VCD can probably be opened directly by PulseView, but is
	33	here converted to a .sr dump.
	34
	35	AUD traffic can be challenging to capture because it is clocked out at the
	36	MCU's clock frequency (20MHz typical). This requires an LA capable of either:
	37
	38	- Timing analysis on 6 channels (clock, sync, data3..0) at >= 80MSps
	39	(40MSps gives very inconsistent results)
	40	- State analysis @ 20MHz, this would be "easy" but cheap hardware like
	41	Logic/Logic16 can't do it.
	42
	43
	44	Data
	45	----
	46
	47	Example to view decoded output:
	48
	49	sigrok-cli -i audgen-01.sr -P aud:audck=AUDCK:naudsync=nAUDSYNC:audata3=AUDATA3:audata2=AUDATA2:audata1=AUDATA1:audata0=AUDATA0
	50