The UART bit information was not transmitted correctly to stacked PDs
if there was an overlap between RX and TX bytes in the data.
self.putbin(rxtx, [rxtx, bytes([b])])
self.putbin(rxtx, [2, bytes([b])])
self.putbin(rxtx, [rxtx, bytes([b])])
self.putbin(rxtx, [2, bytes([b])])
- self.databits = [[], []]
+ self.databits[rxtx] = []
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.