- {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'},
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
- def handle_bit(self, miso, mosi, sck, cs):
+ def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit, save its sample number.
if self.bitcount == 0:
self.startsample = self.samplenum
# If this is the first bit, save its sample number.
if self.bitcount == 0:
self.startsample = self.samplenum
- def find_clk_edge(self, miso, mosi, sck, cs):
+ def find_clk_edge(self, miso, mosi, clk, cs):
if self.have_cs and self.oldcs != cs:
# Send all CS# pin value changes.
self.put(self.samplenum, self.samplenum, self.out_proto,
if self.have_cs and self.oldcs != cs:
# Send all CS# pin value changes.
self.put(self.samplenum, self.samplenum, self.out_proto,
# Sample data on rising/falling clock edge (depends on mode).
mode = spi_mode[self.options['cpol'], self.options['cpha']]
# Sample data on rising/falling clock edge (depends on mode).
mode = spi_mode[self.options['cpol'], self.options['cpha']]
- self.handle_bit(miso, mosi, sck, cs)
+ self.handle_bit(miso, mosi, clk, cs)
def decode(self, ss, es, data):
if self.samplerate is None:
def decode(self, ss, es, data):
if self.samplerate is None:
- self.oldpins, (sck, miso, mosi, cs) = pins, pins
+ self.oldpins, (clk, miso, mosi, cs) = pins, pins
self.have_miso = (miso in (0, 1))
self.have_mosi = (mosi in (0, 1))
self.have_cs = (cs in (0, 1))
# State machine.
if self.state == 'IDLE':
self.have_miso = (miso in (0, 1))
self.have_mosi = (mosi in (0, 1))
self.have_cs = (cs in (0, 1))
# State machine.
if self.state == 'IDLE':
- self.find_clk_edge(miso, mosi, sck, cs)
+ self.find_clk_edge(miso, mosi, clk, cs)