adf435x: Python list idioms in bits sequence accumulation

Use .extend() and .clear() for the Python list during accumulation of a
32bit word's bits sequence. This shall improve readability. Performance
is less of an issue since this decoder's data amount remains small
(32bit entities per SPI transfer).

Comment on the unexpected(?) SPI decoder's BITS ordering when passing
details up to stacked decoders. Raise and keep awareness for this
non-obvious implementation detail during decoder maintenance.

This implementation accumulates bits in the MSB order as they are sent
in SPI frames. Yet keeps the LSB bit order when a completely accumulated
32bit word gets inspected, to reduce the diff size. Bit field extraction
and annotation emission code paths assume a specific timestamp ordering.
The separation of transport and inspection also simplifies maintenance,
should a future SPI decoder provide BITS in their received order.

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 8c31648b873707d929a4fd01b26b078c364b2851..7810190d90f390bde596ae97c3a06fe172430290 100644 (file)
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -135,6 +135,7 @@ class Decoder(srd.Decoder):
 
         if ptype == 'TRANSFER':
             if len(self.bits) == 32:
+                self.bits.reverse()
                 reg_value, reg_pos = self.decode_bits(0, 3)
                 self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
                     ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
@@ -146,8 +147,14 @@ class Decoder(srd.Decoder):
             else:
                 error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
                 self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
-            self.bits = []
+            self.bits.clear()
 
         if ptype == 'BITS':
             _, mosi_bits, miso_bits = data
-            self.bits = mosi_bits + self.bits
+            # Cope with the lower layer SPI decoder's output convention:
+            # Regardless of wire transfer's frame format, .decode() input
+            # provides BITS in the LE order. Accumulate in MSB order here,
+            # and reverse before data processing when 'TRANSFER' is seen.
+            mosi_bits = mosi_bits.copy()
+            mosi_bits.reverse()
+            self.bits.extend(mosi_bits)