]> sigrok.org Git - libsigrokdecode.git/commitdiff
dali: Change 'self.dali' to 'dali'.
authorUwe Hermann <redacted>
Fri, 16 Jun 2017 10:14:28 +0000 (12:14 +0200)
committerUwe Hermann <redacted>
Fri, 16 Jun 2017 10:48:39 +0000 (12:48 +0200)
decoders/dali/pd.py

index 51d82842fcffe3040593e086c27aa5c0b935052a..bdb3fe65bacd447d634575f853976084d05d3a55 100644 (file)
@@ -202,23 +202,23 @@ class Decoder(srd.Decoder):
         bit = 0
         while True:
             # TODO: Come up with more appropriate self.wait() conditions.
-            (self.dali,) = self.wait({'skip': 1})
+            (dali,) = self.wait({'skip': 1})
             if self.options['polarity'] == 'active-high':
-                self.dali ^= 1 # Invert.
+                dali ^= 1 # Invert.
 
             # State machine.
             if self.state == 'IDLE':
                 # Wait for any edge (rising or falling).
-                if self.old_dali == self.dali:
+                if self.old_dali == dali:
                     continue
                 self.edges.append(self.samplenum)
                 self.state = 'PHASE0'
-                self.old_dali = self.dali
+                self.old_dali = dali
                 continue
 
-            if (self.old_dali != self.dali):
+            if self.old_dali != dali:
                 self.edges.append(self.samplenum)
-            elif (self.samplenum == (self.edges[-1] + int(self.halfbit * 1.5))):
+            elif self.samplenum == (self.edges[-1] + int(self.halfbit * 1.5)):
                 self.edges.append(self.samplenum - int(self.halfbit * 0.5))
             else:
                 continue
@@ -238,4 +238,4 @@ class Decoder(srd.Decoder):
                     self.bits.append([self.edges[-3], bit])
                     self.state = 'PHASE0'
 
-            self.old_dali = self.dali
+            self.old_dali = dali