]> sigrok.org Git - libsigrokdecode.git/commitdiff
i2c: also shift first address byte for 10bit slave addresses
authorGerhard Sittig <redacted>
Mon, 17 Jul 2023 16:51:02 +0000 (18:51 +0200)
committerGerhard Sittig <redacted>
Tue, 18 Jul 2023 19:28:44 +0000 (21:28 +0200)
The first address byte in an I2C transfer always carries the R/W bit.
Always shift this byte regardless of 7/10 bit addresses, and always emit
separate annotations for the address value part and the R/W bit part.

decoders/i2c/pd.py

index a2558dd3b6c0531650006b5a837e07deba468d9d..a6c7437d77f7e156768eb6868f06f67f0caf9d09 100644 (file)
@@ -198,11 +198,10 @@ class Decoder(srd.Decoder):
                     self.rem_addr_bytes = 1
                     self.slave_addr_7 = addr_byte >> 1
                     self.slave_addr_10 = None
-            is_seven = self.slave_addr_7 is not None
+            has_rw_bit = self.is_write is None
             if self.is_write is None:
                 read_bit = bool(addr_byte & 1)
-                shift_seven = self.options['address_format'] == 'shifted'
-                if is_seven and shift_seven:
+                if self.options['address_format'] == 'shifted':
                     d = d >> 1
                 self.is_write = False if read_bit else True
             else:
@@ -240,7 +239,7 @@ class Decoder(srd.Decoder):
             texts = [t.format(b = bit_value) for t in texts]
             self.putg(ss_bit, es_bit, cls, texts)
 
-        if cmd.startswith('ADDRESS') and is_seven:
+        if cmd.startswith('ADDRESS') and has_rw_bit:
             # Assign the last bit's location to the R/W annotation.
             # Adjust the address value's location to the left.
             ss_bit, es_bit = self.data_bits[-1][1], self.data_bits[-1][2]