def wait_for_start_bit(self, rxtx, old_signal, signal):
# The start bit is always 0 (low). As the idle UART (and the stop bit)
# level is 1 (high), the beginning of a start bit is a falling edge.
def wait_for_start_bit(self, rxtx, old_signal, signal):
# The start bit is always 0 (low). As the idle UART (and the stop bit)
# level is 1 (high), the beginning of a start bit is a falling edge.